Sun Microsystems UltraSPARC-I User Manual page 66

•
Attempted access using a restricted ASI in non-privileged mode. The MMU
signals a
privileged_action
•
An atomic instruction (including 128-bit atomic load) issued to a memory
address marked uncacheable in a physical cache (that is, with CP=0),
including cases in which the D-MMU is disabled. The MMU signals a
data_access_exception
•
A data access (including FLUSH) with an ASI other than
ASI_{PRIMARY,SECONDARY}_NO_FAULT{_LITTLE} to a page marked with
the NFO (no-fault-only) bit. The MMU signals a
(FT=10 ) for this case.
16
•
Virtual address out of range (including FLUSH) and PSTATE.AM is not set.
The MMU signals a
Table 6-4 D-MMU Operations for Normal ASIs
Condition
PRIV
Opcode
Mode
0
Load 1
0
FLUSH
1
0
1
Store or
Atomic
— 0
1
—
Table 6-5 I-MMU Operations for Normal ASIs
Condition
PRIV Mode TLB Miss
0
IMISS
1
IMISS
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exception for this case.
trap (FT=04 ) for this case.
16
trap (FT=20
data_access_exception
ASI W
PRIM, SEC —
DMISS
PRIM_NF, SEC_NF —
DMISS
PRIM, SEC, NUC —
DMISS
PRIM_NF, SEC_NF —
DMISS
U_PRIM, U_SEC —
DMISS
—
DMISS
—
DMISS
PRIM, SEC 0
DMISS
1
DMISS
PRIM, SEC, NUC 0
DMISS
1
DMISS
U_PRIM, U_SEC 0
DMISS
1
DMISS
BYPASS —
BYPASS —
Behavior
P=0 P=1
OK IEXC
OK
6. MMU Internal Architecture
data_access_exception
) for this case.
16
Behavior
TLB E=0 E=0 E=1
Miss P=0 P=1 P=0
OK DEXC OK
OK DEXC DEXC
OK
OK
OK DEXC OK
OK DEXC DEXC
OK
OK DEXC
DPROT DEXC DPROT
OK DEXC OK
DPROT
OK
DPROT DEXC DPROT
OK DEXC OK
privileged_action
Bypass. No traps when D-MMU enabled,
PRIV=1.
Sun Microelectronics
trap
E=1
P=1
DEXC
DEXC
OK
DEXC
DEXC
DEXC
DEXC
DEXC
DEXC
DPROT
OK
DEXC
DEXC
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