Load / Store Instructions - Sun Microsystems UltraSPARC-I User Manual

UltraSPARC User's Manual
An annulled load use or floating-point use will be treated as a dependent instruc-
tion until the N
FADD f7,f7,f6
Bcc, a (not taken)
FADD f6,f7,f8
FADD f6,f7,f8
If the annulling branch is grouped with a delay slot containing a load use, the
group will pay the full load use penalty even if the load use is annulled. This is
because the branch is not resolved until the use stall is released.
, ,
WR{PR} SAVE SAVED
stalled in the G Stage until earlier annulling branches are resolved, even if they
are not in the delay slot. This means that they cannot be dispatched in the same
group or the first three groups following an annulling branch instruction. For ex-
ample:
Bicc, a
SAVE
,
LDD{A} LDSTUB{A}
delayed control transfer instruction in the E Stage or C Stage. For example:
Bicc
LDD

17.7 Load / Store Instructions

Load / store instructions can be dispatched only if they are in the first three in-
struction slots. One load/store instruction can be dispatched per group. Load /
store instructions other than single group are:
,
LD{D}F{A} ST{B,H,W,X}{A}
, ,
LDD{A} STD{A}
one clock after they are dispatched.
tions for two clocks after they are dispatched.
Loads are not stalled on a cache miss, instead they are enqueued in the load buff-
er until data can be returned. Load data is returned in the order that loads are is-
sued, so a cache miss forces subsequent load hits to be enqueued until the older
load miss data is available.
Sun Microelectronics
290
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Stage of the branch. For example:
2
G E C
G E C
, ,
RESTORE RESTORED
G E C N N
1 2
G
, and
SWAP{A} CAS{X}A
G E C N N N
1 2 3
G E C
, ,
STF{A} STDF{A}
, will not dispatch younger instructions for
LDSTUB{A} SWAP{A}
CAS{X}A
N N N W
1 2 3
N N N W
1 2 3
G flushed
G E C N
1
, , and
RETURN RETRY,
N W
3
E C N N
1 2
are stalled in the G Stage if there is a
W
N N
1 2
LD{SB,SH,SW,UB,UH,UW,X}{A}
, , , ,
JMPL MEMBAR STBAR
will not dispatch younger instruc-
N
2
are
DONE
,
.
PREFETCH{A}