Sun Microsystems UltraSPARC-I User Manual page 243

raSPARC User's Manual
These ASIs allow 8- and 16-bit loads or stores to be performed to the floating-
point registers. Eight-bit loads can be performed to arbitrary byte addresses. For
sixteen bit loads, the least significant bit of the address must be zero, or a
mem_not_aligned trap is taken. Short loads are zero-extended to the full floating
point register. Short stores access the low order 8 or 16 bits of the register.
Little-endian ASIs transfer data in little-endian format in memory; otherwise,
memory is assumed to big-endian. Short loads and stores typically are used with
the FALIGNDATA instruction (see Section 13.5.5, "Alignment Instructions," on
page 214) to assemble or store 64 bits of non-contiguous components.
Traps:
fp_disabled
PA_watchpoint
VA_watchpoint
mem_address_not_aligned
opcode is not LDFA or STDFA)
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(Checked for opcode implied alignment if the