Sun Microsystems UltraSPARC-I User Manual page 258

Table 14-4
Operations
F(sd)TO(ix)
F(sd)TO(ds)
FSQRT(sd)
FADD/SUB(sd)
FSMULD
FMUL(sd)
FDIV(sd)
14.3.1.2 Subnormal Results
If FSR.NS=1, the subnormal results are replaced by zero with the same sign. Un-
derflow and inexact exceptions are signalled in this case. This will cause an
fp_exception_ieee_754
when underflow trap is enabled, otherwise only nxc will be set when inexact trap
is enabled). If FSR.NS=0, then subnormal results generate traps according to
Table 14-5. For FDTOS and FADD, E
rounding. For multiply, E
vide, E is the biased difference of the exponents of the operands.
R
Table 14-5
Operations
FDTOS
FADD/SUB(sd)
FMUL(sd)
FDIV(sd)
14.3.2 Overflow, Underflow, and Inexact Traps (Impdep #3, 55)
UltraSPARC implements precise floating-point exception handling. Underflow is
detected before rounding. Prediction of overflow, underflow and inexact traps for
divide and square root is used to simplify the hardware.
For divide, pessimistic prediction occurs when underflow/overflow can not be
determined from examining the source operand exponents. For divide and
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square root, pessimistic prediction of inexact occurs unless one of the operands is
Subnormal Operand Trapping Cases (NS=0)
One Subnormal Operand
Unfinished trap always
Unfinished trap always
Unfinished trap if no overflow and:
-25 < E (SP);
R
-54 < E (DP)
R
trap if enabled by FSR.TEM (only ufc will be set in FSR.cexc
is the biased sum of the exponents plus one. For di-
R
Subnormal Result Trapping Cases (NS=0)
Trap
Unfinished trap if:
< 1 (SP)
-25 <
E
R
-54 < < 1 (DP)
E
R
Unfinished trap if:
≤ 1 (SP)
-25 <
E
R
≤ 1 (DP)
-54 <
E
R
14. Implementation Dependencies
Two Subnormal
Operands
—
Unfinished trap always
Unfinished trap always
is the biased exponent of the result before
R