Sun Microsystems UltraSPARC-I User Manual page 182

write to the SET_SOFTINT register (ASR 14
interrupt level set. Note that the value written to the SET_SOFTINT register is ef-
fectively ORed into the SOFTINT register. This allows the interrupt handler to set
one or more bits in the SOFTINT register with a single instruction. Read accesses
to the SET_SOFTINT register cause an
cesses to this register will cause a
if (PSTATE.IE=1) and (PIL < n), the processor will receive the highest priority in-
terrupt IRL<n> of the asserted bits in SOFTINT<15:0>.
The processor then takes a trap for the interrupt request, the nucleus will set the
return state to the interrupt handler at that PIL, and return to TL0. In this manner
the nucleus can schedule services at various priorities, and process them accord-
ing to their priority.
When all interrupts scheduled for service at level n have been serviced, the kernel
will write to the CLEAR_SOFTINT register (ASR 15
clear that interrupt. Note that the complement of the value written to the
CLEAR_SOFTINT register is effectively ANDed with the SOFTINT register. This
allows the interrupt handler to clear one or more bits in the SOFTINT register
with a single instruction. Read accesses to the CLEAR_SOFTINT register cause an
trap. Non privileged write accesses to this register will cause a
illegal_instruction
trap.
privileged_opcode
The timer interrupt TICK_INT is equivalent to SOFTINT<14> and has the same
effect.
Note: To avoid a race condition between the kernel clearing an interrupt and
the nucleus setting it, the kernel should reexamine the queue for any valid entries
after clearing the interrupt bit.
Table 9-6 SOFTINT ASRs
ASR ASR
Value Name/Syntax
14 SET_SOFTINT
16
15 CLEAR_SOFTINT
16
16 SOFTINT_REG
16
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) with bit <n> corresponding to the
16
illegal_instruction
trap. When the nucleus returns,
privileged_opcode
Access Description
W Set bit(s) in Soft Interrupt register
W Clear bit(s) in Soft Interrupt register
RW Per-processor Soft Interrupt register
9. Interrupt Handling
trap. Non privileged ac-
) with bit n set, in order to
16
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