Reset And Red_State; Overview - Sun Microsystems UltraSPARC-I User Manual

Reset and RED_state

10.1 Overview

A reset or trap that sets PSTATE.RED (including a trap in RED_state) will clear
the LSU_Control_Register, including the enable bits for the I-Cache, D-Cache,
I-MMU, D-MMU, and virtual and physical watchpoints.
•
The default access in RED_state is noncacheable, so the system must contain
some noncacheable scratch memory.
•
The D-Cache, watchpoints, and D-MMU can be enabled by software in
RED_state, but any trap that occurs will disable them again.
•
The I-MMU and consequently the I-Cache are always disabled in RED_state.
This overrides the enable bits in the LSU_Control_Register.
•
When PSTATE.RED is explicitly set by a software write, there are no side
effects other than disabling the I-MMU. Software must create the appropriate
state itself.
•
Trap when TL = MAXTL
• Trap to error_state; immediately receive watchdog reset (WDR).
•
A Signal Monitor (SIGM) instruction generates an SIR trap on the local
processor.
• Trap to Software-Initiated Reset
•
The External Reset pin generates an XIR trap, which is used for system debug.
•
The caches continue to snoop and maintain coherence if DVMA or other
processors are still issuing cacheable accesses.
•
Reset priorities from highest to lowest are: POR, XIR, WDR, SIR. See the
following sections for explanations of each reset.
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