Sun Microsystems UltraSPARC-I User Manual page 85

raSPARC User's Manual
Due to the implementation of the UltraSPARC pipeline, the MMU can and will
set a TLB entry's used bit as if the entry were hit when the load or store is an an-
nulled or mispredicted instruction. This can be considered to cause a very slight
performance degradation in the replacement algorithm, although it may also be
argued that it is desirable to keep these extra entries in the TLB.
11.3 TSB Pointer Logic Hardware Description
The hardware diagram in Figure 6-16 on page 70 and the code fragment in
Code Example 6-1 on page 71 describe the generation of the 8 Kb and 64 Kb
pointers in more detail.
TSB_Base<63:21>
Pointer
63
( N =TSB_Size)&&TSB_Split
Figure 6-16 Formation of TSB Pointers for 8Kb and 64Kb TTEs
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TSB_Base<20:13>
TSB_Split
TSB_Size<2:0>
TSB Size Logic
7
64k_not8k
43
21 20
TSB Size Logic For Bit N (0 ≤ N ≤ 7)
64k_not8k TSB_Base<13+ N >
N ≥ TSB_Size
64k
VA<24:16> VA<21:13>
64k_not8k
VA<32:22>
0
8 9
13 12
8k
64k
VA<25+ N > VA<22+ N >
64k_not8k
8k
0 0 0 0
3 0