Introduction; Pin Descriptions; E.1 Introduction - Sun Microsystems UltraSPARC-I User Manual

Pin and Signal Descriptions

E.1 Introduction

This Appendix describes the UltraSPARC pins and signals in a general way. Con-
sult the relevant data sheets for detailed information about the electrical and me-
chanical characteristics of the processor, including pin and pad assignments. The
"Bibliography" on page 363 describes the available data sheets and how to obtain
them.
E.2 Pin Descriptions
E.2.1 UltraSPARC Data Buffer (UDB) Interface Pins
Table E-1
Symbol Type
UDB_UEH I
UDB_UEL I
UDB_CEH I
UDB_CEL I
UDB_CNTL<4:0> O
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UltraSPARC Data Buffer (UDB) Interface Pins
Asserted when the High UDB is driving EDATA<127:64>, and it has detected an uncor-
rectable ECC error in that data. Synchronous to system clock.
Asserted when the Low UDB is driving EDATA<63:0>, and it has detected an uncorrect-
able ECC error in that data. Synchronous to system clock.
Asserted when the High UDB is driving EDATA<127:64>, and it has detected and cor-
rected a single-bit error in that data. Synchronous to system clock.
Asserted when the Low UDB is driving EDATA<63:0>, and it has detected and corrected
a single-bit error in that data.
These pins are connected to the UltraSPARC data buffer chips and control the flow of data
between the UDB registers and UltraSPARC. They are asserted with valid EDATA when
UltraSPARC is driving data to UDB. They are asserted the cycle before the UDB should
drive data to UltraSPARC. Synchronous to system clock.
Name and Function
E