Sun Microsystems UltraSPARC-I User Manual page 314

For the preceding two rules, all graphics instructions,
,
FsTOx FiTOd
though a single-precision register is referenced. For example, the following in-
structions can be grouped together:
FORs
FANDs f2, f2, f2
17.8.2 Floating-Point and Graphics Instruction Latencies
Table 17-1 on page 300 documents the latencies for floating-point and graphics in-
structions. For table entries containing two numbers, premature dispatching oc-
curs when the destination and source precision are different, but both are treated
as double because of a graphics or mixed-precision floating-point instruction. To
avoid the pipe flush overhead, software should explicitly force the use instruction
to be at least the latency number of groups after the source instruction. Mixed
precision bypassing is unlikely to occur with floating-point data. Software sched-
uling is only needed for initializing the
tions single results used as part of a double-precision graphics source operand, or
vice versa.
The table uses the following abbreviations:
Abbrev
Graphics A-Class instruction
FGA
Graphics M-Class instruction
FGM
Floating-point A-Class instruction
FPA
Floating-point M-Class instruction
FPM
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, , ,
FxTOs FsTOd FdTOs
f2, f4, f0 G E
G E
Meaning
17. Grouping Rules and Stalls
FDIVs
, and are considered to be double, even
FsMULd
C N N N W
1 2 3
C N N N W
1 2 3
rd register and for graphics instruc-
PDIST
, , ,
FSQRTs FdTOi