Mmu Behavior During Reset, Mmu Disable, And Red_State - Sun Microsystems UltraSPARC-I User Manual

raSPARC User's Manual

7 MMU Behavior During Reset, MMU Disable, and RED_state

During global reset of the UltraSPARC CPU, the following actions occur:
•
No change occurs in any block of the D-MMU.
•
No change occurs in the datapath or TLB blocks of the I-MMU.
•
The I-MMU resets its internal state machine to normal (non-suspended)
operation.
•
The I-MMU and D-MMU Enable bits in the LSU Control Register (see Section
A.6, "LSU_Control_Register," on page 306) are set to zero.
On entering RED_state, the following action occurs:
•
The I-MMU and D-MMU Enable bits in the LSU_Control_Register are set to
zero.
Either MMU is defined to be disabled when its respective MMU Enable bit equals
0; also, the I-MMU is disabled whenever the CPU is in RED_state. The D-MMU is
enabled or disabled solely by the state of the D-MMU Enable bit.
When the D-MMU is disabled it truncates all accesses, behaving as if
ASI_PHYS_BYPASS_EC_WITH_EBIT had been used, notably with side effect bit
(E-bit)=1, P=0 and CP=0. Other attribute bit settings can be found in Section 6.10,
"MMU Bypass Mode," on page 68. However, if a bypass ASI is used while the D-
MMU is disabled, the bypass operation behaves as it does when the D-MMU is
enabled; that is, the access is processed with the E and CP bits as specified by the
bypass ASI.
When the I-MMU is disabled, it truncates all instruction accesses and passes the
physically-cacheable bit (CP=0) to the cache system. The access will not generate
an
instruction_access_exception
When disabled, both the I-MMU and D-MMU correctly perform all LDXA and
STXA operations to internal registers, and traps are signalled just as if the MMU
were enabled. For instance, if a *NO_FAULT load is issued when the D-MMU is
disabled, the D-MMU signals a
es when the D-MMU is disabled have E=1.
Note: While the D-MMU is disabled, data in the D-Cache can be accessed only
using load and store alternates to the UltraSPARC internal D-Cache access ASI.
Normal loads and stores bypass the D-Cache. Data in the D-Cache cannot be
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accessed using load or store alternates that use ASI_PHYS_*.
trap.
data_access_exception
trap (FT=02 ), since access-
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