Sun Microsystems UltraSPARC-I User Manual page 195

raSPARC User's Manual
Table 11-1 E-Cache Error Enable Register Format
Bits
<63:3> Reserved
<2> ISAPEN
<1> NCEEN
<0> CEEN
ISAPEN: If set, an address parity error on an incoming UPA transaction causes a
system fatal error; otherwise, the error is logged and ignored.
NCEEN: If set, an uncorrectable error, time-out, bus error, UDB, or E-Cache data
parity error causes an {
tag parity error causes a system fatal error; otherwise, the error is logged
in the AFSR and ignored.
CEEN: If set, a correctable error detected during a memory read access causes a
correctable_ECC_error
AFSR and ignored. Correctable ECC errors on interrupt vector
transmission are not logged or reported.
.3.2 Asynchronous Fault Status Register
The Asynchronous Fault Status Register (AFSR) logs all errors the have occurred
since its fields are last cleared. The AFSR is updated according to the policy de-
scribed in Table 11-6, "Error Detection and Reporting in AFAR and AFSR," on
page 183.
The AFSR is logically divided into four fields:
•
Bit <32>, the accumulating multiple-error (ME) bit, is set when multiple errors
with the same sticky error bit have occurred except for correctable errors.
Multiple errors of different types are indicated by setting more than one of the
sticky error bits.
•
Bit <31>, the accumulating privilege-error (PRIV), is set when an error occurs
from an access generated by code executing with PSTATE.PRIV = 1. If this bit
is set, system state has been corrupted.
•
Bits <30:20> are sticky error bits that record the most recently detected errors.
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com
These sticky bits accumulate errors that have been detected since the last write
Field
Trap on system address parity error
Trap on TO, BERR, LDP, ETP, EDP, WP, UE, IVUE
Trap on correctable memory read error
instruction, data}_access_error
disrupting trap; otherwise, the error is logged in the
Use
—
trap and an E-Cache
RW
R
RW
RW
RW