Sun Microsystems UltraSPARC-I User Manual page 306

Stores are not stalled on a cache miss. Stores are enqueued in the store buffer un-
til data can be written to the E-Cache SRAM for cacheable accesses, the UDB for
noncacheable accesses, or the internal register for internal ASIs. Store data is
written in the order that stores are issued, so a cache miss forces subsequent store
hits to remain enqueued until the older store miss data is written out.
17.7.1 Load Dependencies and Interaction with Cache Hierarchy
Instructions that reference the result of a load instruction cannot be grouped with
the load instruction or in the following group unless the register is %g0. For ex-
ample:
LDDF [r1], f6 (not enqueued)
FMULd f4, f6, f8
Single-precision floating-point loads lock the double register containing the sin-
gle precision rd for data dependency checking. For example:
LDF [r1], f6 (not enqueued)
FMULs f7, f7, f8
Instructions other than floating-point loads that have the same destination regis-
ter as an outstanding load are treated the same as a source register dependency.
For example:
load
i6 (not enqueued)
ADD i2, i1, i6
When an instruction referencing a load result enters the E Stage and the data is
not yet returned, all instructions in the E Stage and earlier will be stalled. If there
are multiple load uses, then all E Stage and earlier instructions will be stalled un-
til loads that have dependencies return data. E Stage stalls can occur when refer-
encing the result of a signed integer load, a load that misses the D-Cache or a
D-Cache load hit whose data is delayed following one of the two previous cases.
17.7.1.1 Delayed Return Mode
Signed integer loads that hit the D-Cache cause UltraSPARC to enter delayed re-
turn mode. In delayed return mode, an extra clock of delay is added to all return-
ing load data. UltraSPARC remains in delayed return mode until some load other
than a signed integer D-Cache hit can return data in the normal time without col-
liding with a delayed return mode load.
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com
17. Grouping Rules and Stalls
G E C N N
1 2
G E C
G E C N N
1 2
G E C
G E C N N N
1 2 3
G E C N
1
N W
3
N N N
1 2 3
N W
3
N N N
1 2 3
W
N N
2 3
Sun Microelectronics
291