Component Overview - Sun Microsystems UltraSPARC-I User Manual

1.3 Component Overview

Figure 1-1 shows a block diagram of the UltraSPARC processor.
Prefetch and Dispatch Unit (PDU)
Instruction Cache and Buffer
Grouping Logic Integer Reg and Annex
Integer Execution Unit (IEU)
Floating Point Unit (FPU)
FP Multiply
FP
FP Add
Reg
FP Divide
Graphics Unit (GRU)
Figure 1-1
The block diagram illustrates the following components:
•
Prefetch and Dispatch Unit (PDU), including logic for branch prediction
•
16Kb Instruction Cache (I-Cache)
•
Memory Management Unit (MMU), containing a 64-entry Instruction
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Translation Lookaside Buffer (iTLB) and a 64-entry Data Translation
UltraSPARC Block Diagram
1. UltraSPARC Basics
Memory Management Unit (MMU)
iTLB
Load / Store Unit (LSU)
Data Load
Cache Buffer
External Cache Unit (ECU)
Memory Interface Unit (MIU)
System Interconnect
dTLB
Store
Buffer
Ext.
Cache
RAM