Mmu Bypass Mode - Sun Microsystems UltraSPARC-I User Manual

raSPARC User's Manual
9.11 I-/D-Demap Page (Type=0)
Demap Page removes the TTE (from the specified TLB) matching the specified
virtual page number and context register. The match condition with regard to the
global bit is the same as a normal TLB access; that is, if the global bit is set, the
contexts need not match.
Virtual page offset bits <15:13>, <18:13>, and <21:13>, for 64Kb, 512Mb, and 4M
bpage TLB entries, respectively, are stored in the TLB, but do not participate in
the match for that entry. This is the same condition as for a translation match.
Note: Each Demap Page operation removes only one TLB entry. A demap of a
64 Kb, 512 Kb, or 4 Mb page does not demap any smaller page within the
specified virtual address range.
9.12 I-/D-Demap Context (Type=1)
Demap Context removes all TTEs having the specified context from the specified
TLB. If the TTE Global bit is set, the TTE is not removed.

10 MMU Bypass Mode

In a bypass access, the D-MMU sets the physical address equal to the truncated
virtual address; that is, PA<40:0>=VA<40:0>. The physical page attribute bits are
set as shown in Table 6-16.
Table 6-16 Physical Page Attribute Bits for MMU Bypass Mode
ASI_PHYS_USE_EC
ASI_PHYS_USE_EC_LITTLE
ASI_PHYS_BYPASS_EC_WITH_EBIT
ASI_PHYS_BYPASS_EC_WITH_EBIT_LITTLE
Bypass applies to the I-MMU only when it is disabled. See Section 6.7, "MMU Be-
havior During Reset, MMU Disable, and RED_state," on page 54 for details on
the use of bypass when either MMU is disabled.
Compatibility Note:
UltraSPARC
In
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there is no need to use multiple ASIs to fill in the high-order physical address bits,
ASI
the virtual address is longer than the physical address; thus,
Physical Page Attribute Bits
CP IE CV E
1 0 0 0
0 0 0 1
P W NFO Size
0 1 0 8Kb
0 1 0 8Kb