Sun Microsystems UltraSPARC-I User Manual page 325

UltraSPARC User's Manual
Note: To simplify the implementation, read access to the instruction cache fields
(ASIs 60 .. 6F
16 16
Using another type of load causes a
Illegal ASI size). LDDA will update two registers. The useful data is in the odd
register, the contents of the even register are undefined.
A.7.1 I-Cache Instruction Fields
ASI 66 , VA<63:14>=0, VA<13>=IC_set, VA<12:3>=IC_addr, VA<2:0>=0
16
Name: ASI_ICACHE_INSTR
63
Figure A-6 I-Cache Instruction Access Address Format (ASI 66
IC_set: This 1-bit field selects a set (2-way associative).
IC_addr: This 10-bit index <12:3> selects an aligned pair of 32-bit instructions.
63
Figure A-7 I-Cache Instruction Access Data Format (ASI 66
IC_instr: Two 32-bit instruction fields
A.7.2 I-Cache Tag/Valid Fields
ASI 67 , VA<63:14>=0, VA<13>=IC_set, VA<12:5>=IC_addr, VA<4:0>=0
16
Name: ASI_ICACHE_TAG
63
Figure A-8 I-Cache Tag/Valid Access Address Format (ASI 67
IC_set: This 1-bit field selects a set (2-way associative).
IC_addr: This 8-bit index (VA<12:5>) selects a cache tag.
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) must use the LDDA instruction instead of LDXA or LDDFA.
data_access_exception
—
IC_instr 0
33 32
—
trap (with SFSR.FT = 8,
IC_set
IC_addr
14 13 12
)
16
IC_instr 1
)
16
IC_set
IC_addr
14 13 12
)
16
—
3 2 0
0
—
5 4 0