Sun Microsystems UltraSPARC-I User Manual page 300

, and
MULX {U,S}MUL{cc}
number of clocks, depending on the value of the rs1 operand. Four bubbles are
inserted when the upper 60 bits of rs1 are zero, or for signed multiplies when the
upper 60 bits of rs1 are one. Otherwise, an additional bubble is inserted each time
the upper 60 bits of rs1 are not zero (or one for signed multiplies) after arithmetic
right shifting rs1 by two bits. This implies a maximum of 18 bubbles for
19 bubbles for
UMUL{cc},
inserts four bubbles after it is dispatched.
WR{PR}
CANRESTORE, CLEANWIN, OTHERWIN, FPRS, and WSTATE registers, and
from any register are not dispatchable until four clocks after the instruction reach-
es the first slot of the instruction buffer.
Writes to the TICK, PSTATE, and TL registers and
pipeline flush when they reach the W Stage, effectively inserting nine bubbles.
17.5.2 IEU Dependencies
Instructions that have the same destination register (in the same register file) can-
not be grouped together, unless the destination register is %g0. For example:
alu
i6
load
i6
Instructions that reference the result of an IEU instruction cannot be grouped
with that IEU instruction, unless the result is being stored in %g0. For example:
alu
i6
LDX [i6+i1], i8
There are two exceptions to this rule: Integer stores can store the result of an IEU
instruction other than
ample:
alu
r6
store
r6
Also, or
BPicc Bicc
tion codes. For example:
seticc
BPicc
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com
delay dispatching subsequent instructions for a variable
and 34 bubbles for
G E C N
G E C
G E C N
1
G E C
FCMP{LE,NE,GT,EQ}{16,32}
G E C N N N
1 2
G E C N N N
1 2
can be grouped with an older instruction that sets the condi-
G E C N N N
1 2 3
G E C N N N
1 2 3
17. Grouping Rules and Stalls
.
MULX
from the CANSAVE,
RDPR
instructions cause a
FLUSH{W}
N N W
1 2 3
N N N W
1 2 3
N N W
2 3
N N N W
1 2 3
and be in the same group. For ex-
W
3
W
3
W
W
Sun Microelectronics
,
SMUL{cc}
RD
285