Preface; Overview; A Brief History Of Sparc - Sun Microsystems UltraSPARC-I User Manual

Table 1-3
E-Cache Size
512 Kb
1 Mb
2 Mb
4 Mb
8 Mb
16 Mb
The ECU provides overlap processing during load and store misses. For instance,
stores that hit the E-Cache can proceed while a load miss is being processed. The
ECU can process reads and writes indiscriminately, without a costly turn-around
penalty (only 2 cycles). Finally, the ECU handles snoops.
Block loads and block stores, which load/store a 64-byte line of data from mem-
ory to the floating-point register file, are also processed efficiently by the ECU,
providing high transfer bandwidth without polluting the E-Cache.
1.3.9.1 E-Cache SRAM Modes
Different UltraSPARC models support various E-Cache SRAM configurations us-
ing one or more SRAM "modes." Table 1-5 shows the modes that each
UltraSPARC model supports. The modes are described below.
Table 1-4
SRAM Mode
1–1–1
2–2
1–1–1 (Pipelined) Mode:
The E-Cache SRAMS have a cycle time equal to the processor cycle time. The
name "1–1–1" indicates that it takes one processor clock to send the address, one
to access the SRAM array, and one to return the E-Cache data. 1–1–1 mode has a
3 cycle pin-to-pin latency and provides the best possible E-Cache throughput.
2–2 (Register-Latched) Mode:
The E-Cache SRAMS have a cycle time equal to one-half the processor cycle time.
The name "2–2" indicates that it takes two processor clocks to send the address
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and two clocks to access and return the E-Cache data. 2–2 mode has a 4 cycle pin-
Supported E-Cache Sizes
UltraSPARC-I UltraSPARC-II
Supported E-Cache SRAM Modes
UltraSPARC-I UltraSPARC-II
1. UltraSPARC Basics