Test Access Port (Tap) Controller - Sun Microsystems UltraSPARC-I User Manual

raSPARC User's Manual
Table D-1 IEEE 1149.1 Signals
Signal I/O
TDO O
TDI I
TMS I
TCK I
TRST_L I

3 Test Access Port (TAP) Controller

The TAP controller is an synchronous finite state machine with 16-states. Transi-
tions between states occur only at the rising edge of TCK in response to the TMS
signal, or when TRST_L is asserted.
Figure D-1 shows the state machine diagram. The values shown adjacent to state
transitions represents the value of TMS required at the time of a rising edge of
TCK for the transition to occur. Note that the IR states select the instruction regis-
ter and DR states refer to states that may select a test data register, depending on
the active instruction.
3.1 TEST-LOGIC-RESET
The TAP controller enters the TEST-LOGIC-RESET state when the TRST_L pin is
asserted or when the TMS signal is held high for at least five clock cycles (inde-
pendent of the original state of the controller). It will remain in this state while
TMS is held high. In this state the test logic is disabled, the instruction register is
initialized to select the Device ID register.
3.2 RUN-TEST/IDLE
An intermediate controller state between scan operations. If no instruction is se-
lected, all test data registers retain their current state.
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Once the state machine enters the RUN-TEST/IDLE state, it will remain in this
Test data out. This is the scan shift output signal from either the instruction register
or one of the test data registers.
Test data input. This forms the scan shift in signal for the instruction and various test
data registers.
This signal is used to sequence the TAP state machine through the appropriate
sequences. Holding this signal high for at least five clock cycles will force the TAP to
the TEST-LOGIC-RESET state.
Test clock. The inputs TDI and TMS are sampled on the rising edge of TCK and the
TDO output becomes valid after the falling edge of TCK.
The IEEE 1149.1 logic is asynchronously reset when TRST_L goes low.
Description