Floating-Point And Graphic Instructions - Sun Microsystems UltraSPARC-I User Manual

A #LoadStore or #MemIssue will force younger stores to remain out-
MEMBAR
standing until four clocks after all older loads are not outstanding. In PSO or
TSO, stores remain outstanding until four clocks after all older loads are not out-
standing.
STBAR
vent a younger store from leaving the store buffer until five clocks after an
S_REPLY is received from the system for all older noncacheable stores. A store in
TSO will remain outstanding until five clocks after an S_REPLY is received for all
older non-cacheable stores.
Additional clocks are added to the time a cacheable store is outstanding due to
E-Cache misses and delays in arbitration for the D- and E-Caches. A minimum of
twelve clocks plus the UPA latency for accessing the last word of the cache block
will be added to the time a cacheable store is outstanding due to an E-Cache
miss. Back-to-back cacheable store misses can be issued at a maximum rate of
thirteen clocks plus the system latency for the last word of the block. Writeback
of dirty data can be overlapped if the system supports it; the latency to the first
word of read data is at least 18 processor clocks.
Noncacheable stores are removed from the store buffer with the same timing as if
the store were an E-Cache hit, provided that the System Interconnect can accept
them. Depending on the system, up to ten non-\cacheable store requests may be
outstanding past the store buffer. A noncacheable store is considered outstanding
on the interconnect for two system clocks (four to six processor clocks) after the
S_REPLY for the store is received. One noncacheable store (possibly compressed)
can be issued every four clocks to the system interconnect.
, ,
LDSTUB SWAP
#Sync instructions are not dispatched until no older stores are outstanding. The
maximum rate of internal ASI stores or atomics is one every 12 clocks.
cannot be dispatched in the two groups following another
ST{X}FSR
cannot be dispatched in the group after a floating-point store or when a
PDIST
block store is outstanding.

17.8 Floating-Point and Graphic Instructions

Floating-point and graphics instructions that reference floating-point registers are
divided into two classes: A and M. Two of these instructions can be dispatched
together only if they are in different classes.
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, #StoreStore, and
MEMBAR
, store to internal ASI, block store,
CAS{X}A
17. Grouping Rules and Stalls
#MemIssue will pre-
MEMBAR
and
FLUSH, MEMBAR
ST{X}FSR
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