Sun Microsystems UltraSPARC-I User Manual page 89

raSPARC User's Manual
The UltraSPARC Data Buffer isolates UltraSPARC and its E-Cache from the main
system data bus, so the interface can operate at processor speed (reduced load-
ing). The UDB also provides overlapping between system transactions and local
E-Cache transactions, even when the latter needs to use part of the data buffer.
UltraSPARC includes the logic to control the UDB; this provides fast data trans-
fers to and from UltraSPARC or to and from the E-Cache and the system. A sep-
arate address bus and separate control signals support system transactions.
Arbitration
System Address
35+parity
P_REPLY
S
Y
S
S_REPLY
T
E
M
System Data Bus
128 +16 ECC
Figure 7-1 Main UltraSPARC Interfaces
UltraSPARC is both an interconnect master and an interconnect slave.
•
As an interconnect master, UltraSPARC issues read/write transactions to the
interconnect using part of the transaction set (Section 7.5 ). As a master, it also
has physically addressed coherent caches, which participate in the cache
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coherence protocol, and respond to the interconnect for copyback and
Clocks,
Reset, etc.
6
UltraSPARC
5
4
4
UDB
5
Control
UltraSPARC
Data
Buffer
Observability,
JTAG, etc.
15
E-Cache Tag
Address
E$TagAddrBits
E-Cache Tag Data
22+3 state + 4 parity
E-Cache Data
Address
E$DataAddrBits
Byte Write Enable
16
E-Cache Data Bus
128 + 16 parity
E-Cache Tag
RAM
E-Cache Data
RAM