Load Buffer - Sun Microsystems UltraSPARC-I User Manual

CALL, or JMPL instruction. Instructions should not be placed within 256 bytes of
locations with side effects. See Section 16.2.10, "Return Address Stack (RAS)," on
page 272 for other information about JMPLs and RETURNs.
5.3.9 Instruction Prefetch When Exiting RED_state
Exiting RED_state by writing 0 to PSTATE.RED in the delay slot of a JMPL is not
recommended. A noncacheable instruction prefetch may be made to the JMPL
target, which may be in a cacheable memory area. This may result in a bus error
on some systems, which will cause an
masked by setting the NCEEN bit in the ESTATE_ERR_EN register to zero, but
this will mask all non-correctable error checking. To avoid this problem exit
RED_state with DONE or RETRY, or with a JMPL to a noncacheable target ad-
dress.
5.3.10 UltraSPARC Internal ASIs
ASIs in the ranges 46
UltraSPARC states. Stores to these ASIs do not follow the normal memory model
ordering rules. Correct operation requires the following:
•
A MEMBAR #Sync is needed after an internal ASI store other than MMU
ASIs before the point that side effects must be visible. This MEMBAR must
precede the next load or noninternal store. The MEMBAR also must be in or
before the delay slot of a delayed control transfer instruction of any type. This
is necessary to avoid corrupting data.
•
A FLUSH, DONE, or RETRY is needed after an internal store to the MMU
ASIs (ASI 50
before the point that side effects must be visible. Stores to D-MMU registers
other than the context ASIs may also use a MEMBAR #Sync. One of these
instructions must precede the next load or noninternal store. They also must
be in or before the delay slot of a delayed control transfer instruction. This is
necessary to avoid corrupting data.

5.4 Load Buffer

The load buffer allows the load and execution pipelines in UltraSPARC to be de-
coupled; thus, loads that cannot return data immediately will not stall the pipe-
line, but rather, will be buffered until they can return data. For example, when a
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load misses the on-chip D-Cache and must access the E-Cache, the load will be
.. 6F and 76
16 16 16
..52 , 54 ..5F ) or to the IC bit in the LSU control register
16 16 16 16
5. Cache and Memory Interactions
instruction_access_error
..7F are used for accessing internal
16
trap. The trap can be