Processor Pipeline; Introductions - Sun Microsystems UltraSPARC-I User Manual

Processor Pipeline

2.1 Introductions

UltraSPARC contains a 9-stage pipeline. Most instructions go through the pipe-
line in exactly 9 stages. The instructions are considered terminated after they go
through the last stage (W), after which changes to the processor state are irrevers-
ible. Figure 2-1 shows a simplified diagram of the integer and floating-point pipe-
line stages.
Integer Pipeline
Fetch
Floating-Point &
Graphics Pipeline
Figure 2-1
Three additional stages are added to the integer pipeline to make it symmetrical
with the floating-point pipeline. This simplifies pipeline synchronization and ex-
ception handling. It also eliminates the need to implement a floating-point queue.
Floating-point instructions with a latency greater than three (divide, square root,
and inverse square root) behave differently than other instructions; the pipe is
"extended" when the instruction reaches stage N
ation Guidelines" for more information. Memory operations are allowed to pro-
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ceed asynchronously with the pipeline in order to support latencies longer than
Decode Group Execute
Register
UltraSPARC Pipeline Stages (Simplified)
Cache N N
1 2
X X X
1 2 3
. See Chapter 16, "Code Gener-
1
2
N Write
3