References To Model-Specific Information - Sun Microsystems UltraSPARC-I User Manual

raSPARC User's Manual
3 References to Model-Specific Information
Table G-1 lists the pages within the UltraSPARC User's Manual that contain mod-
el-specific information.
Table G-1 UltraSPARC Model-Specific Information
Page I II
4
7
10
10
10
36
73
73
77
77
78
79
80
81
81
82
82
83
96
102
103
104
110
110
112
113
126
128
128
128
130
130
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154
Implementation technologies and cycle times
Number of trap levels
E-Cache sizes
E-Cache SRAM modes
System : Processor clock frequency ratios
Support for the PREFETCH{A} instructions
Number of bits in E-Cache Tag Address
Number of bits in E-Cache Data Address
E-Cache sizes
Number of read buffer entries
Number of Writeback buffer entries
Timing for coherent read hit (1–1–1 Mode)
Timing for coherent read hit (2–2 Mode)
Timing for coherent write hit to M State line (1–1–1 Mode)
Timing for coherent write hit to M State line (2–2 Mode)
Timing for coherent write hit with E-to-M State transsition (1–1–1 Mode)
Timing overlap for tag read / data write for coherent write (1–1–1 Mode)
Read-to-write bus turnaround penalty (1–1–1 Mode)
Support for the PREFETCH{A} instructions
Number of outstanding ReadToShare transactions
Number of outstanding ReadToOwn transactions
Number of outstanding ReadToDiscard transactions
Number of outstanding NonCachedRead transactions
Number of outstanding NonCachedBlockRead transactions
Worst-Case Delay Between S_REQ and P_REPLY when NDP=1
Number of outstanding Writeback transactions
Number of outstanding read transactions
Limited transaction types before Writeback
Limited number of outstanding transactions in a class
Programmatically limiting the number of outstanding transactions in a class
Number of outstanding Writeback / dirty victim read transaactions
Number of outstanding Writeback / dirty victim read transaactions
MCAP field of UPA_CONFIG register
Description