Ultrasparc Interconnect Transaction Overview - Sun Microsystems UltraSPARC-I User Manual

raSPARC User's Manual
In Figure 7-18, the SC becomes
L P D
AST ORT RIVER
Req<0>
SC Request
SYSADDR
Figure 7-18 Arbitration: SC Becomes C

5 UltraSPARC Interconnect Transaction Overview

The are four interconnect transaction categories:
1. P_REQ transaction request from UltraSPARC to the system on the
SYSADDR bus. These transactions initiate activity on the interconnect.
P_REQ transactions are further subdivided into coherent requests for
cacheable memory accesses, noncacheable P_REQ transactions, and
interrupt vector accesses. Coherent read/write requests transfer 64-byte
blocks, which corresponds to the E-Cache block size. Partial stores are
supported to noncacheable locations only. The interconnect does not
support read-modify-write requests, so atomic loads and stores can be
performed only to cacheable memory.
UltraSPARC splits P_REQ transactions into two independent classes:
• Class 0 contains read transactions due to cacheable misses and block
loads
• Class 1 contains Writeback requests, WriteInvalidate requests, block
stores, interrupt requests, noncached read requests (other than block
loads), and noncached write requests.
SC must strongly order transactions from each processor within each Class.
2. S_REQ transaction request from the system to the processor on the
SYSADDR bus; it is either a copyback/invalidate in response to some
coherent P_REQ or a slave read of the processor ID register.
3. P_REPLY acknowledgment generated by the processor to the system on
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point-to-point unidirectional wires. It is generated in response to a
.
C D
URRENT RIVER
0 0
Request Arbitration
Asserted
D
URRENT RIVER
0 0
Cycle 1
First Cycle
Occurs of Packet
0
Cycle 2