Sun Microsystems UltraSPARC-I User Manual page 229

UltraSPARC User's Manual
13.5.5 Alignment Instructions
opcode
ALIGNADDRESS
ALIGNADDRESS_LITTLE
FALIGNDATA
Format (3):
10 rd
31 30 29 25
Suggested Assembly Language Syntax
alignaddr reg
alignaddrl reg
faligndata freg
Description:
ALIGNADDRESS adds two integer registers, rs1 and rs2, and stores the result,
with the least significant 3 bits forced to zero, in the integer rd register. The least
significant 3 bits of the result are stored in the GSR.alignaddr_offset field.
ALIGNADDRESS_LITTLE is the same as ALIGNADDRESS, except that the 2's
complement of the least significant 3 bits of the result is stored in
GSR.alignaddr_offset.
Note: ALIGNADDRL is used to generate the opposite-endian byte ordering for
a subsequent FALIGNDATA operation.
FALIGNDATA concatenates two 64-bit floating-point registers, rs1 and rs2, to
form a 16-byte value; it stores the result in the 64-bit floating-point rd register. Rs1
is the upper half and rs2 is the lower half of the concatenated value. Bytes in this
value are numbered from most significant to least significant, with the most sig-
nificant byte being byte 0. Eight bytes are extracted from this value, where the
most significant byte of the extracted value is the byte whose number is specified
by the GSR.alignaddr_offset field.
A byte-aligned 64-bit load can be performed as follows:
Code Example 13-3 Byte-Aligned 64-bit Load
alignaddr
ldd
ldd
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opf
0 0001 1000
Calculate address for misaligned data access
0 0001 1010
Calculate address for misaligned data access,
little-endian
0 0100 1000
Perform data alignment for misaligned data
110110 rs1
24 19 18
, reg , reg
rs1 rs2 rd
, reg , reg
rs1 rs2 rd
, freg , freg
rs1 rs2 rd
Address, Offset, Address
[Address], %f0
[Address + 8], %f4
operation
opf
14 13 5
rs2
4 0