Table 6-6
Condition for Instruction Access
Table 6-7
Condition for Data Access
Opcode
LD/ST/Atomic/FLUSH
LD/ST/Atomic Alternate
with specified ASI not
ending in "_LITTLE"
LD/ST/Atomic Alternate
with specified ASI
ending in '_LITTLE"
1
Accesses to non-translating ASIs are always made in "big endian" mode, regardless of the setting of D-MMU.IE. See Section 8.3,
"Alternate Address Spaces," on page 146 for information about non-translating ASIs.
The context register used by the data and instruction MMUs is determined from
the following table. A comprehensive list of ASI values can be found in the ASI
map in Section 8.3, "Alternate Address Spaces," on page 146. The context register
selection is not affected by the endianness of the access.
Table 6-8
ASI Value
ASI_*NUCLEUS*
ASI_*PRIMARY*
ASI_*SECONDARY*
All other ASI values
a. Any ASI name containing the string "NUCLEUS".
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b. Any ASI name containing the string "PRIMARY".
ASI Mapping for Instruction Accesses
PSTATE.TL
0
> 0
ASI Mapping for Data Accesses
PSTATE.
PSTATE.
D-MMU.
TL
CLE
0
0
1
0
> 0
1
Don't Care
Don't Care
Don't Care
Don't Care
I-MMU and D-MMU Context Register Usage
a
Nucleus (0000
b
c
(Not applicable, no translation)
6. MMU Internal Architecture
Resulting Action
Endianness
ASI Value (in SFSR)
Big
ASI_PRIMARY
Big
ASI_NUCLEUS
Access Processed with:
Endianness
IE
0
Big
1
Little
0
Little
1
Big
0
Big
1
Little
0
Little
1
Big
1
0
Big
Specified ASI value from immediate
1
1
Little
0
Little
Specified ASI value from immediate
1
Big
Context Register
hard-wired)
16
Primary
Secondary
ASI Value
(Recorded in SFSR)
ASI_PRIMARY
ASI_PRIMARY_LITTLE
ASI_NUCLEUS
ASI_NUCLEUS_LITTLE
field in opcode or ASI register
field in opcode or ASI register
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