Sun Microsystems UltraSPARC-I User Manual page 259

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raSPARC User's Manual
enabled, an
fp_exception_other
System software will properly handle these cases and resume execution. If the ex-
ception is not enabled, the actual result status is used to update the aexec bits of
the fsr.
Note: Major performance degradation may be observed while running with the
inexact exception enabled.
.3.3 Quad-Precision Floating-Point Operations (Impdep #3)
All quad-precision floating-point instructions, listed in Table 14-6, cause an
fp_exception_other
emulated in system software.
Table 14-6
Unimplemented Quad-Precision Floating-Point Instructions
Instruction
F{s,d}TOq
F{i,x}TOq
FqTO{s,d}
FqTO{i,x}
FCMP{E}q
FMOVq
FMOVqcc
FMOVqr
FABSq
FADDq
FDIVq
FdMULq
FMULq
FNEGq
FSQRTq
FSUBq
.3.4 Floating Point Upper and Lower Dirty Bits in FPRS Register
The FPRS_dirty_upper (DU) and FPRS_dirty_lower (DL) bits in the Floating-
Point Registers State (FPRS) Register are set when an instruction that modifies the
corresponding upper and lower half of the floating-point register file is dis-
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patched. Floating-point register file modifying instructions include floating-point
(with FSR.ftt=2,
(with FSR.ftt=3,
unimplemented_FPop
Convert single-/double- to quad-precision floating-point
Convert 32-/64-bit integer to quad-precision floating-point
Convert quad- to single-/double-precision floating-point
Convert quad-precision floating-point to 32-/64-bit integer
Quad-precision floating-point compares
Quad-precision floating-point move
Quad-precision floating-point move, if condition is satisfied
Quad-precision floating-point move if register match condition
Quad-precision floating-point absolute value
Quad-precision floating-point addition
Quad-precision floating-point division
Double- to quad-precision floating-point multiply
Quad-precision floating-point multiply
Quad-precision floating-point negation
Quad-precision floating-point square root
Quad-precision floating-point subtraction
) trap is generated.
unfinished_FPop
) trap. These operations are
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