Sun Microsystems UltraSPARC-I User Manual page 256

14.2.3 Integer Multiply and Divide
Integer multiplications (MULScc, SMUL{cc}, MULX) and divisions (SDIV{cc},
UDIV{cc}, UDIVX) are executed directly in hardware.
Multiplications are done 2 bits at a time with early exit when the final result is
generated. Divisions use a 1-bit non-restoring division algorithm.
Note: For best performance, the smaller of the two operands of a multiply
should be the rs1 operand.
14.2.4 Version Register (Impdep #2, 13, 101, 104)
Consult the product data sheet for the content of the Version Register for an im-
plementation. For the state of this register after resets, see Table 10-1, "Machine
State After Reset and in RED_state," on page 172.
Table 14-2
Bits
<63:48>
<47:32>
<31:24>
<23:16>
<15:8>
<7:5>
<4:0>
manuf: 16-bit manufacturer code, 0017
manufacturer of an UltraSPARC CPU.
impl: 16-bit implementation code, 0010
UltraSPARC-class CPU. Table 14-3 shows the VER.impl values for each
UltraSPARC model.
Table 14-3
VER.impl
mask: 8-bit mask set revision number that identifies the mask set revision of this
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UltraSPARC. This is subdivided into a 4 bit major mask number <31:28>
Version Register Format
Field
manuf Manufacturer identification
impl Implementation identification
mask Mask set version
Reserved —
maxtl Maximum trap level supported
Reserved —
maxwin Maximum number of windows of integer register file.
VER.impl Values by UltraSPARC Model
UltraSPARC-I UltraSPARC-II
0010 0011
16
14. Implementation Dependencies
Use
(TI JEDEC number), that identifies the
16
, that uniquely identifies an
16
16
RW
R
R
R
R
R
R
R