Sun Microsystems UltraSPARC-I User Manual page 355

UltraSPARC User's Manual
Table E-4 External Cache Interface Pins (Continued)
Symbol Type
BYTEWE_L<15:0> O Byte write enables for the E-Cache SRAMs. Bit 0 controls EDATA<127:120>. Bit 15 con-
trols EDATA<7:0>. Byte write control is necessary because the first-level data cache is
write-through. Synchronous to processor clock.
1
ECAD<17:0> O Address for E-Cache data SRAMS. Corresponds to physical address <21:4>. Allows a
maximum 4mbyte E-Cache. Synchronous to processor clock.
2
ECAT<15:0> O Address for E-Cache tag SRAMS. Corresponds to physical address <21:6>. Allows a
maximum 4Mb E-Cache. Synchronous to processor clock.
DSYN_WR_L O Write enable for E-Cache data SRAMS. Active low. Synchronous to processor clock.
DOE_L O Active low operation enable for all E-Cache data SRAM reads and writes. Synchronous
to processor clock.
TSYN_WR_L O Write enable for E-Cache tag SRAMS. Active low. Synchronous to processor clock.
TOE_L O Active low operation enable for all E-Cache tag SRAM reads and writes. Active low.
Synchronous to processor clock.
1.
ECAD<19:0> for UltraSPARC-II: corresponds to Physical Address <23:4>
2.
ECAT<17:0> for UltraSPARC-II: corresponds to Physical Address <23:6>
E.2.5 Clock Interface Pins
Table E-5 Clock Interface Pins
Symbol Type
CLKA, CLKB I
SYSCLKA, SYSCLKB I
1
SCLK_MODE I
2
LOOP_CAP I
3
PHASE_DET_CLK I
4
ECACHE_22_MODE I
5
MCAP<3:0> I
1.
SCLK_MODE is present only on UltraSPARC-I.
2.
LOOP_CAP is present only on UltraSPARC-I.
3.
PHASE_DET_CLK is present only on UltraSPARC-II.
4.
ECACHE_22_MODE is present only on UltraSPARC-II.
5.
MCAP is present only on UltraSPARC-II.
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Name and Function
Name and Function
These pins provide UltraSPARC with its primary differential PECL clock source. Full
details of clock requirements are presented in another chapter.
Buffered differential versions of the PECL system clock, which is a synchronous one
half or one third submultiple of the primary clock. They are used to generate the
phase signal, which allows UltraSPARC to synchronize communication to the sys-
tem and UDBs.
Asserted if the system clock frequency is one third of the processor clock frequency,
deasserted if the system clock frequency is one half of the processor clock frequency.
Provision for external PLL loop filter capacitor. Currently not needed.
Used only for testing PLL Bypass mode.
Asserted if 2–2 (Register-latch) SRAMS are used in the E-Cache. Deasserted for 1–1–
1 (pipelined) E-Cache SRAMS. Hardwired externally.
Implementation-dependent module capability bits. May be used to indicate speed
range of the module. Hardwired externally.