Sun Microsystems UltraSPARC-I User Manual page 197

raSPARC User's Manual
Table 11-3 E-Cache Data Parity Syndrome Bit Orderings
Byte
Address
F
16
E
16
D
16
C
16
B
16
A
16
9
16
8
16
7
16
6
16
5
16
4
16
3
16
2
16
1
16
0
16
Table 11-4 E-Cache Tag Parity Syndrome Bit Orderings
E-Cache Tag
Syndrome Bit
Bus Bits
<7:0>
<15:8>
<21:16>
<24:22>
.3.3 Asynchronous Fault Address Register
This register is valid when one of the Asynchronous Fault Status Register (AFSR)
error status bits that capture address is set (correctable or uncorrectable memory
ECC error, bus time-out or bus error). The address corresponds to the first occur-
rence of the highest priority error in AFSR that captures address (see Section
11.5.1, "AFAR Overwrite Policy," on page 185). Address capture is reenabled by
clearing all corresponding error bits in AFSR. If software attempts to write to
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these bits at the same time as an error that captures address occurs, the error ad-
E- Cache Data
Syndrome Bit
Bus Bits
<7:0>
<15:8>
<23:16>
<31:24>
<39:32>
<47:40>
<55:48>
<63:56>
<71:64>
<79:72>
<87:80> 10
<95:88> 11
<103:96> 12
<111:104> 13
<119:112> 14
<127:120> 15
0
1
2
3
0
1
2
3
4
5
6
7
8
9