Floating-Point Control; Watchpoint Support - Sun Microsystems UltraSPARC-I User Manual

raSPARC User's Manual
This control register is accessed through ASR 18
register cause a
and in RED_state," on page 172 for the state of this register after reset.
63
Figure A-1 Dispatch Control Register (ASR 18
MS IEU.multi_scalar—Multi-Scalar Dispatch Control. If cleared, instruction
dispatch is forced to a single instruction per group.

4 Floating-Point Control

Two state bits (PSTATE.PEF and FPRS.FEF) in the SPARC-V9 architecture provide
the means to disable direct floating-point execution. If either field is cleared, an
trap is taken when a floating-point instruction is encountered.
fp_disabled
Note: Graphics instructions that use the floating-point register file and
instructions that read or update the Graphic Status Register (GSR) are treated as
floating-point instructions. They cause an
FPRS.FEF is cleared. See Section 13.5, "Graphics Instructions," on page 198 for
more information.

5 Watchpoint Support

UltraSPARC implements "break before"
stopped immediately before the watchpoint memory location is accessed. Table
A-1 on page 305 lists ASIs that are affected by the two watchpoint traps. For
128-bit atomic load and 64-byte block load and store, a
ed only if the watchpoint overlaps the lowest addressed 8 bytes of the access.
Note: In order to avoid trapping infinitely, software should emulate the
instruction at the watched address and execute a DONE instruction or turn off
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the watchpoint before exiting a
trap. See also Table 10-1, "Machine State After Reset
privileged_opcode
watchpoint
. Nonprivileged accesses to this
16
—
)
16
trap if either PSTATE.PEF or
fp_disabled
traps; instruction execution is
watchpoint
watchpoint
trap handler.
MS
0
1
trap is generat-