Graphics Instructions - Sun Microsystems UltraSPARC-I User Manual

raSPARC User's Manual
RDASR format:
10 rd
31 30 29
WRASR format:
10 rd
10 rd
31 30 29
Suggested Assembly Language Syntax
rd %gsr, reg
wr reg
rs1
Accesses to this register cause an
FPRS.FEF is zero.
Figure 13-2 shows the format of the GSR.
63
Figure 13-2 GSR Format (ASR 10
scale_factor: Shift count in the range 0 .. 15, used by PACK instructions for pixel
formatting.
alignaddr_offset: Least significant three bits of the address computed by the last
ALIGNADDRESS or ALIGNADDRESS_LITTLE instruction. See Section 13.5.5,
"Alignment Instructions," on page 214.
Traps:
fp_disabled

.5 Graphics Instructions

All instruction operands are in floating-point registers, unless otherwise speci-
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fied. This provides the maximum number of registers (32 double-precision) and
op3
25 24 19 18
op3
op3
25 24 19 18
rd
, reg_or_imm , %gsr
fp_disabled
—
)
16
rs1 i=0
12
14 13
i=0
rs1
i=1
rs1
14 13 12
trap if either PSTATE.PEF or
scale_factor
7 6
—
0
—
rs2
simm13
5 4
0
alignaddr_offset
3 2 0