Sun Microsystems UltraSPARC-I User Manual page 80

The Data In and Data Access registers are the means of reading and writing the
TLB for all operations. The TLB Data In register is used for TLB-miss and TSB-
miss handler automatic replacement writes; the TLB Data Access register is used
for operating system and diagnostic directed writes (writes to a specific TLB en-
try). Both types of registers have the same format, as follows:
V Size NFO
63 62 61 60
Figure 6-12 MMU I-/D-TLB Data In/Access Registers
Refer to the description of the TTE data in Section 6.2, "Translation Table Entry
(TTE)," on page 41, for a complete description of the above data fields.
Operations to the TLB Data In register require the virtual address to be set to ze-
ro. The format of the TLB Data Access register virtual address is as follows:
63
Figure 6-13 MMU TLB Data Access Address, in Alternate Space
TLB Entry: The TLB Entry number to be accessed, in the range 0 .. 63.
The format for the Tag Read register is as follows:
63
Figure 6-14 I-/D-MMU TLB Tag Read Registers
I/D VA<63:13>: The 51-bit virtual page number. Page offset bits for larger page
sizes are stored in the TLB and returned for a Tag Read register read, but
ignored during normal translation; that is, VA<15:13>, VA<18:13>, and
VA<21:13> for 64Kb, 512Kb and 4Mb pages, respectively. Note that this
field is sign-extended based on VA<43>.
I/D Context<12:0>: The 13-bit context identifier.
An ASI store to the TLB Data Access register initiates an internal atomic write to
the specified TLB Entry. The TLB entry data is obtained from the store data, and
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com
the TLB entry tag is obtained from the current contents of the TLB Tag Access
IE Soft2 Diag
59 58 50 49 41 40
—
VA<63:13>
6. MMU Internal Architecture
Soft L
PA<40:13>
13 12 7 6
9 8
13 12
CP CV E P W G
5 4 3 2 1 0
TLB Entry 000
3 2
0
Context<12:0>
0