Sun Microsystems UltraSPARC-I User Manual page 113

raSPARC User's Manual
6.2 Cache Coherence Model
UltraSPARC supports a variety of cache coherent system implementations.
UltraSPARC can be used in a system that keeps a non-uniform copy of the
E-Cache tags. Non-uniform means that it does not maintain all five of the MOESI
states. It is possible to build a set of duplicate tags (Dtags) with 2, 3, or 4 states,
with various mappings of the MOESI states onto the reduced states. There can be
performance or implementation advantages specific to a system depending on
the Dtag description.
It is possible to build a simpler system without Dtags. In systems of this type, any
cache-coherent activity from another memory user must first interrogate
UltraSPARC to see if the memory line is in use. If the line is in use, the
UltraSPARC is asked to change the line's MOESI state.
In systems with or without Dtags, the goal is to implement a write-invalidate
cache coherency protocol.
Because UltraSPARC allows coherent read misses and Writebacks to complete in-
dependently, a typical external controller, (SC or system controller) must main-
tain some transient state during the window defined by the outstanding read and
Writeback. It is possible, however, to avoid maintaining this state by making the
read with Writeback complete atomically; this is described later.
Figure 7-21 illustrates a system that uses Dtags to maintain cache coherence; the
system contains multiple UltraSPARCs, one Dtag cache for each processor, a Sys-
tem Controller, and one Dtag Transient Buffer (DtagTB) within the SC for each
Dtag cache. The drawing also shows the Etag and Writeback buffer within each
UltraSPARC.
Each DtagTB contains the same number of entries as the number of Writeback
buffer entries in each UltraSPARC, which is model dependent. The DtagTB acts
as the n+mth Dtag entry, where n is the number of Etag entries and m is the num-
ber of Writeback buffer entries. The DtagTB temporarily holds the Dtag state for
either the new line or the victim (Writeback) line when a cache miss displaces a
dirty block from the E-Cache. Conceptually, it is easier to design an SC that keeps
the victim address in the DtagTB, but it may be difficult to get the tag from the
Dual tags, depending on the specific implementation.
The SC must manage the transient buffer carefully. Since DtagTB contains lines
that may need to return data in response to coherent reads, SC must interrogate it
whenever it would interrogate the Dtags. Alternatively, the SC could block other
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coherent activity to that index until both the read and Writeback complete, so the