Sun Microsystems UltraSPARC-I User Manual page 309

UltraSPARC User's Manual
instructions are held in the G Stage until three clocks after the N
LDD{A}
or until older loads have returned data. If
on an N Stage or earlier load, the instruction will be canceled in the W Stage and
2
fetched again. It will then be held in the G Stage until three clocks after older
loads have returned data.
,
FLUSH{W} {F}MOVr
ASI (4x-6x, 76, 77),
#Sync instructions cannot be dispatched until three clocks after older loads
BAR
have returned data. The instruction is stalled in the G Stage until the N
the earliest outstanding load, if the load is not enqueued. For example:
load
(not enqueued)
SAVE
LD{SB,SH,SW,UB,UH,UW,X}{A}
,
LD{X}FSR MEMBAR
Stage if there are already nine outstanding loads. A load is considered outstand-
ing from the clock that it enters the E Stage through the clock that it returns data.
17.7.2 Store Dependencies
A store is considered outstanding from the clock that it enters the E Stage until
two clocks after the data leaves the store buffer. Data leaves the store buffer when
the write is issued to the E-Cache SRAM for cacheable accesses, UDB for non-
cacheable accesses, and internal register for internal ASI. If there is no extra delay,
a noncacheable store or cacheable store that misses the D-Cache will be outstand-
ing for ten clocks after it is dispatched. An internal ASI or cacheable store that
hits the D-Cache will be outstanding for eleven clocks after it is dispatched. If the
last two stores in the store buffer are writing to the same 16-byte block and both
are ready to go to the E-Cache, the store buffer will compress the two entries into
one. This reduces the number of outstanding stores by one. Compression will be
repeated as long as the last two entries are ready to go and are compressible.
,
ST{B,H,W,X}{A}
,
STBAR MEMBAR
there are already eight outstanding stores. A block store counts as eight outstand-
ing stores when it is dispatched.
If bits 13..4 of a store's effective memory address are the same as an older load in
the load buffer, the store will remain outstanding until four clocks after the load
is not outstanding.
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, , ,
MOVcc RDFPRS STD{A}
, , RETURN, DONE, RETRY, WRPR, and
SAVE RESTORE
G E C
, ,
LD{D}F{A}
#MemIssue and
MEMBAR
, , ,
STF{A} STDF{A} STD{A} LDSTUB{A}
#StoreStore, and
MEMBAR
is dispatched and a miss occurs
LDD{A}
, loads and stores from an internal
N N N W
1 2 3
G E C N
, ,
LDD{A} LDSTUB{A} SWAP{A}
#StoreLoad are held in the G
, ,
SWAP{A} CAS{X}A
#LoadStore are not dispatched if
Stage,
3
MEM-
Stage of
3
1
, ,
CAS{X}A
, ,
FLUSH