raSPARC User's Manual
ATA pins 338 to 339
ATA signals 341, 343
e handling instructions 219
e mask encoding 220
little-endian 221
GE16 instruction 219
GE16L instruction 219
GE32 instruction 219
GE32L instruction 219
GE8 instruction 219
GE8L instruction 219
PAR pins 338 to 339
PAR signals 341, 343
ble D-MMU (DM) field of LSU_Control_
Register 19, 307
ble Floating-Point (PEF) field of PSTATE
register 198, 304
ble I-MMU (IM) field of LSU_Control_
Register 307
ianness 42
rgy Star compliance 327
anced security environment 240
D pin 338, 341
D signal 342
or Correcting Code (ECC)
generated and checked by UDB 76
or Correcting Code (ECC) byte addresses
within quadword
illustrated 76
or Correction Code (ECC) 75
generation and checking 10
or correction code (ECC) 18
or_state 169, 236
or_state processor state 171
ATE_ERR_EN Register 170
ATE_ERR_EN register 252
lusive (E) state 80 to 82
cute (E) Stage 14
illustrated 11
cution (E) Stage 14
PAND instruction 206
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T_EVENT signal 342 to 343
extended floating-point pipeline 11
extended instructions 3, 253
Extended Interrupt Target ID 117
external cache 4, 18
External Cache (E-Cache) 8, 14
External Cache Unit (ECU) 8
illustrated 5
external power-down (EPD) signal 196, 328
External Reset pin 169
Externally Initiated Reset (XIR) 169, 171, 239
trap 158
externally_initiated_reset
F
FALIGNDATA instruction 214, 228
false errors 176
FAND instruction 215
FANDNOT1 instruction 215
FANDNOT1S instruction 215
FANDNOT2 instruction 215
FANDNOT2S instruction 215
FANDS instruction 215
fast_data_access_MMU_miss
fast_data_access_protection
252
fast_instruction_access_MMU_miss
159, 252
fatal errors 175
Fatal Errors (P_FERR) 119, 130
Fault Address field of SFAR 61
Fault Type (FT) field of SFSR register 31, 34 to 36,
58, 248, 303, 310
Fault Type (ft) field of SFSR register 49
Fault Valid (FV) field of SFSR register 60
Fault_Address, see Fault_Address field of SFAR
register
fcc, see Floating-Point Condition Code (fcc) field of
FSR register
fcc0, see Floating-Point Condition Code 0 (fcc0) field
of FSR register
fcc1, see Floating-Point Condition Code 1 (fcc1) field
of FSR register
fcc2, see Floating-Point Condition Code 2 (fcc2) field
F
trap 47 to 48, 60, 159
trap 47 to 48, 63, 159,
trap 47 to 48, 60,
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