Sun Microsystems 2060 Manuals

Manuals and User Guides for Sun Microsystems 2060. We have 1 Sun Microsystems 2060 manual available for free PDF download: Hardware Engineering Manual

Sun Microsystems 2060 Hardware Engineering Manual (405 pages)

CPU Board

Brand: Sun Microsystems | Category: Computer Hardware | Size: 14 MB

Table of Contents
3
Preface
20
Chapter 1 An Ovelview of Thesun-3Architecture

23
- 1.1. Cpu
  23
- Control Space Devices - FC3
  23
- 1.7. Memory Management Unit
  23
- Device Space
  23
- Memory Space (TYPED Space)
  23
- CPU Resets and Timeout
  23
- Table 1-3 TYPE2 Space
  27
- Table 1-5 On-Board Interrupts
  27
Chapter 2 VME Compliance

29
- Options
  29
Chapter 3 Block Diagram

32
Chapter 4 Mechanical Specifications

35
- Connectors
  35
- Switches
  35
- Table 5-4 CPU Space Cycles
  40
- Table 5-5 Coprocessor Designation
  40
- Figure 5-1 Virtual Address Space
  40
Chapter 5 68020,68881 Floating Point Coprocessor, and Associated Circuitry

42
- Power-On Circuitry
  49
Chapter 7 Response Synchronizer - U206

51
Chapter 8 Reset Pal U201 and User Reset Switch U205

53
- U205 User Reset Switch
  53
- U201 Reset PAL
  53
- Figure 8-1 Sun-3 Connectors on the 2060 CPU Board
  54
- U201 Input Signals
  55
- Figure 8-2 U201 Pinout
  55
Chapter 9 U202 and U203 Bus Error PAL and Register

57
- U202 Inputs
  57
- Pinout Ofu202 PAL
  57
  - Figure 9-1 U202 Pinout
    59
  - 9.3. U202 Output Signals
    60
  - U203 Bus Error Register
    63
Chapter 10 U204 DSACK PAL

64
Chapter 12 Interrupt Circuitry - U302-U304 Pals, U305

76
- Interrupt Request Cycle
  76
- Interrupt Acknowledge Cycle
  77
- Figure 12-2 Interrupt Acknowledge Cycle
  78
- Figure 12-3 Interrupt and Acknowledge Cycle
  79
- Priority
  80
  - U302 Pinout
    82
  - U302 Input Signals
    82
  - Figure 12-4 U302 Pinout
    82
  - Table 12-4 Lower Priority Acknowledge Signals
    84
  - U303 Higher-Priority Encoder
    87
    
    U303 Pinout
    87
    
    U303 Output Signals
    88
    
    Table 12-6 Higher-Level Priority Acknowledge Signals
    89
    
    Figure 12-6 U304 Pinout
    92
    
    U304 Output Sigilals
    93
  - Spurious Interrupt
    95
  - Ethernet Controller and Spurious Interrupts
    96
Chapter 13 ATE Pulldowns - U407

98
Chapter 14 Clock Generation

100
- Pinout Ofu400
  101
  - Pal
    101
  - Figure 14-1 U400 Pinout
    101
- U400 Input Sigjlals
  102
- 14.3. U400 Output Signals
  103
- U401 Flip-Flops 1()4
  104
- 14.5. U402 Flip-Flops
  104
Chapter 15 Pal U408

105
- IS.I. Pinout Ofu408 PAL
  105
- Figure 15-1 U408 Pinout
  106
Chapter 16 Sun-3 Memory Management Unit (MMU)

107
Chapter 17 Context Register - U509

110
- Table 17-1 U509 Context Register-Description
  111
- Figure 17-1 Context Bits and Virtual Address
  111
Chapter 18 Segment Map - U500:08

114
- Segment Map Read and Write Cycles
  114
- Segment Map RAM Control Signals
  117
Chapter 19 Page Map RAM

119
- Table 19-2 MMU Statistics Bits
  120
- Table 19-4 Byte Selection in the Page Map RAM
  121
Chapter 20 Statistics Control PAL - U611

123
- 20.1. U611 Input Signals
  124
- 20.2. U611 Output Signals
  125
Chapter 21 MMU Validation and Decode PAL

128
- 21.1. U612 Input Signals
  128
- U612 Output Signals
  129
Chapter 22 P2 Bus Control and Address Buffers

135
- U700 Comparator
  135
- U703:01 P2 Address Buffers
  135
- 22.3. U704 Control Signal Buffer
  135
- Aliases
  135
- Table 22-1 U700 Comparator
  135
Chapter 23 Parity Circuitry

138
- Parity Address Latch -U811:08
  139
- Parity Generator/Checkers -U807:04
  139
- 23.3. U803 Multiplexer
  140
- U812 Parity Check PAL
  141
  - U812 Input Signals
    141
  - U812 Output Signals
    141
  - U802 Parity Control PAL
    144
    
    U802 Input Signals
    144
    
    Table 23-2 Parity State Diagram - Description of the States
    146
    
    Figure 23-1 U802 Pinout
    147
  - Memory Errorregister-U801
    149
  - Byte Select Buffer (and Address Bit Driver) - U813
    150
  - Parity Data Buffer- U3112
    150
Chapter 24 MOS Bus Devices

157
- Table 24-2 U901 Control Counter States
  160
- Table 24-3 U901 Wait Counter States
  160
- U904 Pinout
  167
- U902 MOS Write Buffer
  172
- MOS Read and Write Cycles
  173
- U903 MOS Read Buffer
  173
- Mouse and Keyboard SCC
  174
  - U405 and U2207 Baud Rate Clock
    175
  - Transmit Data Path
    175
  - Receive Data Path
    175
- Serial Ports a and B - Ttya and Nyb
  175
  - Transmit Data Path
    176
- EEPROM Aild EPROM
  176
- TTL Bus Accesses
  188
- U1401 TTL Bus Device Decoder
  191
  - Output Signals of the Ul401 PAL
    193
  - Table 25-4 Byte Selection in the Page Map RAM
    199
  - Figure 25-4 U1402 Pinout
    200
  - U 1402 Input Signals
    201
  - Figure 25-5 U1403 Pinout
    207
- Ethernet Control Register
  211
  - U1407 Ethernet Control Read Buffer
    212
- System Enable Register
  212
  - U1406 System Enable Write Register
    212
  - U1408 System Enable Read Register
    213
- U1410 Diagnostics Register
  213
- 25.9. U1409 ID Prom
  213
- U1404 P2-To-TTL Data Buffer
  213
- U2905 and U2906 User DVMA Enable Register
  214
- U203 Bus Error Register
  214
  - Figure 26-1 U1504 Pinout
    222
    
    Figure 26-2 U1502 Pinout
    224
    
    Figure 26-3 U1503 Pinout
    228
    
    Figure 26-4 Handshaking in the P2 Interface State Machine
    232
    
    Figure 28-1 U2704 Pinout
    255
    
    Input and Output Signals
    300
    
    Figure 29-2 U2806 Pinout
    276
    
    Terminology for V1\1E Master Controller
    277
    
    CPU Freeze Cycles
    279
    
    CPU Cycles
    292
    
    DVMA Cycles
    292
  - Transitions from IDLE State
    261
  - Transitions from BUSREQ State
    262
  - Transitions from MASTER_NG State
    263
  - Transitions from the Busgranf State
    265
Chapter 29 VME Master Interface

273
- Deadlock Resolution
  273
- VME Master Controller PAL U2806
  275
- Figure 30-1 U2907 Pinout
  283
- Figure 30-2 U2904 Pinout
  287
Chapter 30 VME Slave Interface

281
- VME Slave Address Latches, U2901-2 and U2911-13
  281
- VME Slave Address Decoder U2907
  282
- A Generic DVMA Cycle
  296
- Ethernet Hold
  297
- The DVMA Strobe PAL (U241 0)
  298
Chapter 31 VME Data Buffers, U3000 to U3006

292
Chapter 32 Direct Virtual Memory Access

295
- Figure 32-1 U2410 Pinout
  299
Chapter 33 Sample Cycles

302
- V1Vffi Slave Cycles
  302
- Lock Mode Cycles
  308
- VME Device Ends P2 Bus Lock
  309
Chapter 34 RAS Decodepals- U3100 Andu3102

312
- U3100 and U3102 Pinouts
  312
- U3100 and U3I02 Outputs
  312
- U3100 Output Signals
  312
- U3102 Output Signals
  312
Chapter 35 CAS Decode PAL-U3104

320
- U3104 Input Signals
  320
- U3104 Output Signals
  320
- U3104 Pinout
  320
- Figure 35-1 U3104 Pinout
  321
Chapter 36 Control Buffers - U3105 and U3115

325

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Sun Microsystems 2060 Manuals

Sun Microsystems 2060 Hardware Engineering Manual (405 pages)

Table of Contents

Chapter 1 An Ovelview of Thesun-3Architecture

Chapter 2 VME Compliance

Chapter 3 Block Diagram

Chapter 4 Mechanical Specifications

Chapter 5 68020,68881 Floating Point Coprocessor, and Associated Circuitry

Chapter 7 Response Synchronizer - U206

Chapter 8 Reset Pal U201 and User Reset Switch U205

Chapter 9 U202 and U203 Bus Error PAL and Register

Chapter 10 U204 DSACK PAL

Chapter 12 Interrupt Circuitry - U302-U304 Pals, U305

Chapter 13 ATE Pulldowns - U407

Chapter 14 Clock Generation

Chapter 15 Pal U408

Chapter 16 Sun-3 Memory Management Unit (MMU)

Chapter 17 Context Register - U509

Chapter 18 Segment Map - U500:08

Chapter 19 Page Map RAM

Chapter 20 Statistics Control PAL - U611

Chapter 21 MMU Validation and Decode PAL

Chapter 22 P2 Bus Control and Address Buffers

Chapter 23 Parity Circuitry

Chapter 24 MOS Bus Devices

Chapter 29 VME Master Interface

Chapter 30 VME Slave Interface

Chapter 31 VME Data Buffers, U3000 to U3006

Chapter 32 Direct Virtual Memory Access

Chapter 33 Sample Cycles

Chapter 34 RAS Decodepals- U3100 Andu3102

Chapter 35 CAS Decode PAL-U3104

Chapter 36 Control Buffers - U3105 and U3115

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