Terminology And Definitions - Intel 810A3 Design Manual

Introduction
•
Chapter 9, "Third-Party Vendor
various third-party vendors who provide products to support the Intel
•
Appendix A, "PCI
devices and functions supported by the Intel
component PCI Vendor ID, Device ID, Revision ID, Class code, Sub-class code, and
Programming Interface code values. In addition, component APIC interrupt and ISA/PCI
IRQs are listed.
1.1.1

Terminology and Definitions

Term
Aggressor
AGTL+
Bus Agent
Core power rail
Corner
1-2
Information"— This chapter includes information regarding
Devices/Functions/Registers/Interrupts"— This appendix lists the PCI
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Definition
A network that transmits a coupled signal to another network is called
the aggressor network.
The processor system bus uses a bus technology called AGTL+, or
Assisted Gunning Transceiver Logic. AGTL+ buffers are open-drain
and require pull-up resistors for providing the high logic level and
termination. The processor AGTL+ output buffers differ from GTL+
buffers with the addition of an active pMOS pull-up transistor to "assist"
the pull-up resistors during the first clock of a low-to-high voltage
transition. Additionally, the processor Single Edge Connector (S.E.C.)
cartridge contains 56 Ω pull-up resistors to provide termination at each
bus load.
A component or group of components that, when combined, represent a
single load on the AGTL+ bus.
A power rail that is only on during full-power operation. These power
rails are on when the PSON signal is asserted to the ATX power supply.
The core power rails that are distributed directly from the ATX power
supply are: ±5V, ±12V and +3.3V.
Describes how a component performs when all parameters that could
impact performance are adjusted to have the same impact on
performance. Examples of these parameters include variations in
manufacturing process, operating temperature, and operating voltage.
The results in performance of an electronic component that may change
as a result of corners include (but are not limited to): clock to output
time, output driver edge rate, output drive current, and input drive
current. Discussion of the "slow" corner would mean having a
component operating at its slowest, weakest drive strength performance.
Similar discussion of the "fast" corner would mean having a component
operating at its fastest, strongest drive strength performance. Operation
or simulation of a component at its slow corner and fast corner is
expected to bound the extremes between slowest, weakest performance
and fastest, strongest performance.
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810A3 chipset.
810A3 chipset. Also included are a list of
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Intel 810A3 Chipset Design Guide