Tx Pattern Generator; Functional Description; Ports And Attributes - Xilinx Virtex-6 FPGA User Manual

TX Pattern Generator

Functional Description

The GTH transceiver pattern generator block can generate the industry-standard PRBS
patterns listed in
Table 3-11: PRBS Pattern

Ports and Attributes

There are no ports in the TX pattern generator.
Table 3-12
Table 3-12: TX Pattern Generator Attributes
Attribute
PRBS_CFG_LANE0
PRBS_CFG_LANE1
PRBS_CFG_LANE2
PRBS_CFG_LANE3
Virtex-6 FPGA GTH Transceivers User Guide
UG371 (v2.0) February 16, 2010
Table 3-11.
Name Polynomial
6
PRBS7 1 + X + X
5
PRBS9 1 + X + X
9
PRBS11 1 + X + X
18
PRBS23 1 + X + X
28
PRBS31 1 + X + X
defines the TX pattern generator attributes.
Type
16-bit Hex [15:4]: Reserved. Use the recommended values from the Virtex-6 FPGA
GTH Transceiver Wizard.
[3:2]: PRBS generate width
2'b11: 20b
2'b10: 16b
Others: Reserved
[1:0]: PRBS checker width
2'b11: 20b
2'b10: 16b
Others: Reserved
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Length of
Sequence
7 7
2 – 1 bits Characteristics are similar to 8B/10B data.
9 9
2 – 1 bits Used by 10GBASE-LRM.
11 11
2 – 1 bits Used by 10BASE-KR link training.
23 23
2 – 1 bits PRBS23 is often used for non-8B/10B
encoding schemes. This is one of the
recommended test patterns in the SONET
specification.
31 31
2 – 1 bits Characteristics are similar to 64B/66B data.
Description
TX Pattern Generator
Description
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