Omron SYSMAC CS Series Operation Manual page 505

Index Registers
1,2,3...
Index Register
Initialization
1,2,3...
IOM Hold Bit Operation
every cycle. Refer to 1-1-5 Inputting Data in Operands in the Instructions
Reference for details.
Example
MOVR 000013 IR0
LD P_Off
OUT ,IR0+
With the above programming, OUT will turn OFF CIO 000013 and IR0 will
be incremented to point to CIO 000014.
MOVR 000013 IR0
LD P_Off
SET ,IR0+
SET is executed only when the input condition is ON. With the above pro-
gramming, SET will not be executed and IR0 will not be incremented.
2. The PLC memory addresses are listed in the diagram above, but it isn't
necessary to know the PLC memory addresses when using Index Regis-
ters.
Since some operands are treated as word data and others are treated as bit
data, the meaning of the data in an Index Register will differ depending on the
operand in which it is used.
1. Word Operand:
MOVR(560) 0000
MOV(021) D00000
When the operand is treated as a word, the contents of the Index Register
are used "as is" as the PLC memory address of a word.
In this example MOVR(560) sets the PLC memory address of CIO 0002 in
IR2 and the MOV(021) instruction copies the contents of D00000 to
CIO 0002.
2. Bit Operand:
MOVR(560) 000013
SET +5 , IR2
When the operand is treated as a bit, the leftmost 7 digits of the Index Reg-
ister specify the word address and the rightmost digit specifies the bit num-
ber. In this example, MOVR(560) sets the PLC memory address of
CIO 000013 (0C000D hex) in IR2. The SET instruction adds +5 from bit 13
to this PLC memory address, so it turns ON bit CIO 000102.
The Index Registers will be cleared in the following cases:
1. The operating mode is changed from PROGRAM mode to RUN/MONITOR
mode or vice-versa and the IOM Hold Bit is OFF.
2. The PLC's power supply is cycled and the IOM Hold Bit is OFF or not pro-
tected in the PLC Setup.
If the IOM Hold Bit (A50012) is ON, the Index Registers won't be cleared
when a FALS error occurs or the operating mode is changed from PROGRAM
mode to RUN/MONITOR mode or vice-versa.
If the IOM Hold Bit (A50012) is ON, and the PLC Setup's "IOM Hold Bit Status
at Startup" setting is set to protect the IOM Hold Bit, and if the Index Registers
are not set to be shared between tasks (default setting), Index Registers will
be held in the following way when power is interrupted. For tasks that were
completed before power was interrupted, the values for the cycle during which
power was interrupted will be held. For tasks that were not completed before
power was interrupted, the values for the cycle before the cycle during which
IR2
, IR2
,IR2
Section 9-22
467