Sequence Output Instructions - Omron SYSMAC CS Series Operation Manual

Instruction Execution Times and Number of Steps
Instruction Mnemonic
LOAD NOT LD NOT
!LD NOT
AND AND
!AND
AND NOT AND NOT
!AND NOT
OR OR
!OR
OR NOT OR NOT
!OR NOT
AND LOAD AND LD
OR LOAD OR LD
NOT NOT
CONDITION UP
ON
CONDITION DOWN
OFF
LOAD BIT LD TST
TEST
LOAD BIT LD TSTN
TEST NOT
AND BIT AND TSTN 351
TEST NOT
OR BIT TEST OR TST
OR BIT TEST OR TSTN
NOT

10-5-2 Sequence Output Instructions

Instruction Mnemonic
OUTPUT OUT
!OUT
516
Code Length
(steps)
CPU6@H
--- 1 0.02
--- 2 +21.14
+45.1
--- 1 0.02
--- 2 +21.14
+45.1
--- 1 0.02
--- 2 +21.14
+45.1
--- 1 0.02
--- 2 +21.14
+45.1
--- 1 0.02
--- 2 +21.14
+45.1
--- 1 0.02
--- 1 0.02
520 1 0.02
521 3 0.3
522 4 0.3
350 4 0.14
351 4 0.14
4 0.14
350 4 0.14
351 4 0.14
Note When a double-length operand is used, add 1 to the value shown in the length
column in the following table.
Code Length
(steps)
CPU-6@H
(See note.)
--- 1 0.02
--- 2 +21.37
+49.3
ON execution time (µs)
CPU4@H CPU6@
0.04 0.04
+21.16 +21.16
+45.1 +45.1
0.04 0.04
+21.16 +21.16
+45.1 +45.1
0.04 0.04
+21.16 +21.16
+45.1 +45.1
0.04 0.04
+21.16 +21.16
+45.1 +45.1
0.04 0.04
+21.16 +21.16
+45.1 +45.1
0.04 0.04
0.04 0.04
0.04 0.04
0.42 0.46
0.42 0.46
0.24 0.25
0.24 0.25
0.24 0.25
0.24 0.25
0.24 0.25
ON execution time (µs)
CPU-4@H CPU-6@
0.04 0.17
+21.37 +21.37
+49.3 +49.3
Section 10-5
Conditions
CPU4@
008 ---
+21.16 Increase for CS
Series
+45.1 Increase for
C200H
0.08 ---
+21.16 Increase for CS
Series
+45.1 Increase for
C200H
0.08 ---
+21.16 Increase for CS
Series
+45.1 Increase for
C200H
0.08 ---
+21.16 Increase for CS
Series
+45.1 Increase for
C200H
0.08 ---
+21.16 Increase for CS
Series
+45.1 Increase for
C200H
0.08 ---
0.08 ---
0.08 ---
0.54 ---
0.54 ---
0.37 ---
0.37 ---
0.37 ---
0.37 ---
0.37 ---
Conditions
CPU-4@
0.21 ---
+21.37 Increase for CS
Series
+49.3 Increase for
C200H