Power-On / Reset Timing - Epson S1V3G340 Hardware Specification

6. Electrical Characteristics
HVDD
RVDD
NRESET
CLKI / OSCI
Symbol
t
1
t
2
t
3
*1
Note: The circuit must be initialized with NRESET after initiating power supply. The internal circuit state cannot
be guaranteed when switching the HVDD from off to on, due to power supply noise and other factors.
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6.4.3

Power-on / Reset Timing

Figure 6.3 Power on / reset timing
Minimum delay from the HVDD power-on to
the CLKI/OSCI rising edge before NRESET
release.
The minimum NRESET assertion on system power up.
NRESET synchronization time
(Number of clock cycles before the reset signal is applied internally.)
T is the CLKI / OSCI clock period.
OSC
t
1
t
t
3
2
Item
Input clock source: CLKI
Input clock source: OSCI
EPSON
t
3
Min. Max. Unit
100 - μs
10 - ms
T
OSC
2 -
(*1)
T
OSC
2 -
(*1)
S1V3G340 Hardware Specification
(Rev. 1.0)