AM1808
SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
AHCLKR/X (Falling Edge Polarity)
AHCLKR/X (Rising Edge Polarity)
ACLKR/X (CLKRP = CLKXP = 0)
ACLKR/X (CLKRP = CLKXP = 1)
AFSR/X (Bit Width, 0 Bit Delay)
AFSR/X (Bit Width, 1 Bit Delay)
AFSR/X (Bit Width, 2 Bit Delay)
AFSR/X (Slot Width, 0 Bit Delay)
AFSR/X (Slot Width, 1 Bit Delay)
AFSR/X (Slot Width, 2 Bit Delay)
AXR[n] (Data In/Receive)
A.
For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP
receiver is configured for falling edge (to shift data in).
B.
For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP
receiver is configured for rising edge (to shift data in).
140
Peripheral Information and Electrical Specifications
2
1
2
3
(A)
(B)
6
5
8
7
A0
A1
Figure 6-30. McASP Input Timings
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4
4
A30 A31
B0 B1
B30 B31 C0 C1
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C2 C3
C31