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3 Device Overview
3.1
Device Characteristics
Table 3-1
provides an overview of the device. The table shows significant features of the device, including
the capacity of on-chip RAM, peripherals, and the package type with pin count.
HARDWARE FEATURES
DDR2/mDDR Controller
EMIFA
Flash Card Interface
EDMA3
Timers
UART
SPI
2
I
C
Peripherals
Multichannel Audio Serial Port [McASP]
Not all peripherals pins
are available at the
Multichannel Buffered Serial Port [McBSP]
same time (for more
10/100 Ethernet MAC with Management Data I/O
detail, see the Device
Configurations section).
eHRPWM
eCAP
USB 2.0 (USB0)
USB 1.1 (USB1)
General-Purpose Input/Output Port
LCD Controller
SATA Controller
Universal Parallel Port (uPP)
Video Port Interface (VPIF)
PRU Subsystem (PRUSS)
Size (Bytes)
On-Chip Memory
Organization
JTAG BSDL_ID
DEVIDR0 Register
CPU Frequency
MHz
Core (V)
Voltage
I/O (V)
Packages
Product Preview (PP),
(1)
Product Status
Advance Information (AI),
or Production Data (PD)
(1) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 2010–2014, Texas Instruments Incorporated
Table 3-1. Characteristics of the Device
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SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
AM1808
DDR2, 16-bit bus width, up to 156 MHz
Mobile DDR, 16-bit bus width, up to 150 MHz
Asynchronous (8/16-bit bus width) RAM, Flash,
16-bit SDRAM, NOR, NAND
MMC and SD cards supported
64 independent channels, 16 QDMA channels,
2 channel controllers, 3 transfer controllers
4 64-Bit General Purpose (each configurable as 2 separate
32-bit timers, one configurable as Watch Dog)
3 (each with RTS and CTS flow control)
2 (Each with one hardware chip select)
2 (both Master/Slave)
1 (each with transmit/receive, FIFO buffer, 16 serializers)
2 (each with transmit/receive, FIFO buffer, 16)
1 (MII or RMII Interface)
4 Single Edge, 4 Dual Edge Symmetric, or
2 Dual Edge Asymmetric Outputs
3 32-bit capture inputs or 3 32-bit auxiliary PWM outputs
High-Speed OTG Controller with on-chip OTG PHY
Full-Speed OHCI (as host) with on-chip PHY
9 banks of 16-bit
1 (Supports both SATA I and SATAII)
1 (video in and video out)
2 Programmable PRU Cores
168KB RAM
ARM
16KB I-Cache
16KB D-Cache
8KB RAM (Vector Table)
64KB ROM
ADDITIONAL MEMORY
128KB RAM
0x0B7D_102F
ARM926 375 MHz (1.2V) or 456 MHz (1.3V)
1.2 V nominal for 375 MHz version
1.3 V nominal for 456 MHz version
1.8V or 3.3 V
13 mm x 13 mm, 361-Ball 0.65 mm pitch, PBGA (ZCE)
16 mm x 16 mm, 361-Ball 0.80 mm pitch, PBGA (ZWT)
375 MHz versions - PD
456 MHz versions - PD
AM1808
AM1808
1
1
Device Overview
7
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