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AM1808
SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
NO.
1
tc(REFCLK)
2
tw(REFCLKH)
3
tw(REFCLKL)
6
tsu(RXD-REFCLK)
7
th(REFCLK-RXD)
8
tsu(CRSDV-REFCLK)
9
th(REFCLK-CRSDV)
10
tsu(RXER-REFCLK)
11
th(REFCLKR-RXER)
(1) RMII is not supported at operating points below 1.1V nominal.
(2) Per the RMII industry specification, the RMII reference clock (RMII_MHZ_50_CLK) must have jitter tolerance of 50 ppm or less.
Table 6-103. Switching Characteristics Over Recommended Operating Conditions for EMAC RMII
NO.
4
td(REFCLK-TXD)
5
td(REFCLK-TXEN)
(1) RMII is not supported at operating points below 1.1V nominal.
RMII_MHz_50_CLK
RMII_TXEN
RMII_TXD[1:0]
RMII_RXD[1:0]
RMII_CRS_DV
RMII_RXER
192
Peripheral Information and Electrical Specifications
Table 6-102. Timing Requirements for EMAC RMII
Cycle Time, RMII_MHZ_50_CLK
Pulse Width, RMII_MHZ_50_CLK High
Pulse Width, RMII_MHZ_50_CLK Low
Input Setup Time, RXD Valid before RMII_MHZ_50_CLK High
Input Hold Time, RXD Valid after RMII_MHZ_50_CLK High
Input Setup Time, CRSDV Valid before RMII_MHZ_50_CLK High
Input Hold Time, CRSDV Valid after RMII_MHZ_50_CLK High
Input Setup Time, RXER Valid before RMII_MHZ_50_CLK High
Input Hold Time, RXER Valid after RMII_MHZ_50_CLK High
PARAMETER
Output Delay Time, RMII_MHZ_50_CLK High to TXD Valid
Output Delay Time, RMII_MHZ_50_CLK High to TXEN Valid
1
2
3
5
4
8
Figure 6-49. RMII Timing Diagram
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(2)
6
7
9
10
11
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AM1808
www.ti.com
(1)
1.3V, 1.2V, 1.1V
UNIT
MIN
TYP
MAX
20
ns
7
13
ns
7
13
ns
4
ns
2
ns
4
ns
2
ns
4
ns
2
ns
(1)
1.3V, 1.2V, 1.1V
UNIT
MIN
TYP
MAX
2.5
13
ns
2.5
13
ns
5
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