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Texas Instruments AM335 Series Technical Reference Manual

Arm cortex-a8

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AM335x ARM

Cortex™-A8 Microprocessors

®

(MPUs)

Technical Reference Manual

Literature Number: SPRUH73H

October 2011 – Revised April 2013

Table of Contents

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Page 1 AM335x ARM Cortex™-A8 Microprocessors ® (MPUs) Technical Reference Manual Literature Number: SPRUH73H October 2011 – Revised April 2013...
Page 2 SGX530 Connectivity Attributes ..............5.2.2 SGX530 Clock and Reset Management ....................5.2.3 SGX530 Pin List ....................Functional Description .................... 5.3.1 SGX Block Diagram Contents SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 3 Clock Generation and Management ..................... 8.1.7 Reset Management ..................8.1.8 Power-Up/Down Sequence ......................8.1.9 IO State ................. 8.1.10 Voltage and Power Domains SPRUH73H – October 2011 – Revised April 2013 Contents Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 4 9.3.39 smrt_ctrl Register (offset = 6A0h) [reset = 0h] ..........9.3.40 mpuss_hw_debug_sel Register (offset = 6A4h) [reset = 0h] ..........9.3.41 mpuss_hw_dbg_info Register (offset = 6A8h) [reset = 0h] Contents SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 5 9.3.91 ddr_data0_ioctrl Register (offset = 1440h) [reset = 0h] ........... 9.3.92 ddr_data1_ioctrl Register (offset = 1444h) [reset = 0h] ........................Interconnects ....................... 10.1 Introduction SPRUH73H – October 2011 – Revised April 2013 Contents Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 6 12.3.3 Averaging of Samples (1, 2, 4, 8, and 16) 1026 ..............12.3.4 One-Shot (Single) or Continuous Mode 1026 ...................... 12.3.5 Interrupts 1026 Contents SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 7 ........13.5.20 LCDDMA_FB1_CEILING Register (offset = 50h) [reset = 0h] 1151 ............13.5.21 SYSCONFIG Register (offset = 54h) [reset = 0h] 1152 SPRUH73H – October 2011 – Revised April 2013 Contents Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 8 1488 ................... 15.1.3 PWMSS Registers 1489 ..................15.2 Enhanced PWM (ePWM) Module 1494 ....................15.2.1 Introduction 1494 ..................15.2.2 Functional Description 1498 Contents SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 9 17.1.5 MAILBOX Registers 3245 ........................17.2 Spinlock 3306 ..................17.2.1 SPINLOCK Registers 3306 ....................Multimedia Card (MMC) 3344 ......................18.1 Introduction 3345 SPRUH73H – October 2011 – Revised April 2013 Contents Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 10 ................. 19.4.1 UART Programming Model 3496 ................... 19.4.2 IrDA Programming Model 3502 ......................19.5 UART Registers 3505 ....................19.5.1 UART Registers 3505 Contents SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 11 21.4.1 I2C Registers 3716 ................Multichannel Audio Serial Port (McASP) 3768 ......................22.1 Introduction 3769 ................... 22.1.1 Purpose of the Peripheral 3769 SPRUH73H – October 2011 – Revised April 2013 Contents Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 12 23.3.14 Configuration of Message Objects 3899 ..................23.3.15 Message Handling 3902 ....................23.3.16 CAN Bit Timing 3907 ................. 23.3.17 Message Interface Register Sets 3915 Contents SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 13 ............23.4.49 IF3DATA Register (offset = 150h) [reset = 0h] 3983 ............23.4.50 IF3DATB Register (offset = 154h) [reset = 0h] 3984 SPRUH73H – October 2011 – Revised April 2013 Contents Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 14 4096 ....................26.1.3 Memory Map 4097 .................. 26.1.4 Start-up and Configuration 4101 ......................26.1.5 Booting 4103 ..................26.1.6 Fast External Booting 4112 Contents SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 15 4153 ......................Debug Subsystem 4156 ....................27.1 Functional Description 4157 ..............27.1.1 Debug Suspend Support for Peripherals 4157 ......................Revision History 4159 SPRUH73H – October 2011 – Revised April 2013 Contents Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 16: Table Of Contents
..................6-36. INTC_ISR_CLEAR2 Register ..................6-37. INTC_PENDING_IRQ2 Register ..................6-38. INTC_PENDING_FIQ2 Register ..................... 6-39. INTC_ITR3 Register ....................6-40. INTC_MIR3 Register List of Figures SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 17 7-39. NAND Page Mapping and ECC: Pooled Spare Schemes ........7-40. NAND Page Mapping and ECC: Per-Sector Schemes, with Separate ECC SPRUH73H – October 2011 – Revised April 2013 List of Figures Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 18 ....................7-86. GPMC_BCH_RESULT6_i ....................7-87. OCMC RAM Integration ................7-88. DDR2/3/mDDR Memory Controller Signals ................7-89. DDR2/3/mDDR Subsystem Block Diagram List of Figures SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 19 7-133. DDR PHY Data Macro 0/1 Write Leveling Init Ratio Register ( ..............DATA0/1_REG_PHY_WRLVL_INIT_RATIO_0) 7-134. DDR PHY Data Macro 0 Write Leveling Init Mode Ratio Selection Register SPRUH73H – October 2011 – Revised April 2013 List of Figures Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 20 8-21. Warm Reset Sequence (External Warm Reset Source) ............. 8-22. Warm Reset Sequence (Internal Warm Reset Source) ................8-23. CM_PER_L4LS_CLKSTCTRL Register List of Figures SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 21 ................8-68. CM_PER_TIMER6_CLKCTRL Register ................8-69. CM_PER_MMC1_CLKCTRL Register ................8-70. CM_PER_MMC2_CLKCTRL Register ................8-71. CM_PER_TPTC1_CLKCTRL Register ................8-72. CM_PER_TPTC2_CLKCTRL Register SPRUH73H – October 2011 – Revised April 2013 List of Figures Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 22 .................. 8-117. CM_DIV_M5_DPLL_CORE Register ................8-118. CM_CLKMODE_DPLL_MPU Register ................8-119. CM_CLKMODE_DPLL_PER Register ................8-120. CM_CLKMODE_DPLL_CORE Register ................8-121. CM_CLKMODE_DPLL_DDR Register List of Figures SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 23 ..................8-166. PRM_IRQENABLE_MPU Register ..................8-167. PRM_IRQSTATUS_M3 Register ..................8-168. PRM_IRQENABLE_M3 Register ..................8-169. RM_PER_RSTCTRL Register ..................8-170. PM_PER_PWRSTST Register SPRUH73H – October 2011 – Revised April 2013 List of Figures Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 24 ....................9-21. init_priority_1 Register ......................9-22. mmu_cfg Register ......................9-23. tptc_cfg Register ......................9-24. usb_ctrl0 Register ......................9-25. usb_sts0 Register List of Figures SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 25 ..................9-70. tpcc_evt_mux_44_47 Register ..................9-71. tpcc_evt_mux_48_51 Register ..................9-72. tpcc_evt_mux_52_55 Register ..................9-73. tpcc_evt_mux_56_59 Register ..................9-74. tpcc_evt_mux_60_63 Register SPRUH73H – October 2011 – Revised April 2013 List of Figures Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 26 11-23. Block Move Example PaRAM Configuration ..................11-24. Subframe Extraction Example ............... 11-25. Subframe Extraction Example PaRAM Configuration ....................11-26. Data Sorting Example List of Figures SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 27 ..................11-73. Event Clear Register High (ECRH) ....................11-74. Event Set Register (ESR) ..................11-75. Event Set Register High (ESRH) SPRUH73H – October 2011 – Revised April 2013 List of Figures Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 28 11-122. Source Active Source Address B-Reference Register (SASRCBREF) 1010 ........11-123. Source Active Destination Address B-Reference Register (SADSTBREF) 1011 ..............11-124. Destination FIFO Options Register (DFOPTn) 1012 List of Figures SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 29 ....................12-38. STEPDELAY8 Register 1072 ....................12-39. STEPCONFIG9 Register 1073 ....................12-40. STEPDELAY9 Register 1074 ..................... 12-41. STEPCONFIG10 Register 1075 SPRUH73H – October 2011 – Revised April 2013 List of Figures Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 30 ................... 13-25. LIDD_CS1_CONF Register 1136 ................... 13-26. LIDD_CS1_ADDR Register 1137 .................... 13-27. LIDD_CS1_DATA Register 1138 ....................13-28. RASTER_CTRL Register 1139 List of Figures SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 31 ....................14-29. TX_IDVER Register 1258 ....................14-30. TX_CONTROL Register 1259 .................... 14-31. TX_TEARDOWN Register 1260 ....................14-32. RX_IDVER Register 1261 SPRUH73H – October 2011 – Revised April 2013 List of Figures Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 32 ....................14-78. CPTS_IDVER Register 1310 ................... 14-79. CPTS_CONTROL Register 1311 .................... 14-80. CPTS_TS_PUSH Register 1312 ..................14-81. CPTS_TS_LOAD_VAL Register 1313 List of Figures SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 33 ................14-127. P0_CPDMA_TX_PRI_MAP Register 1363 ................14-128. P0_CPDMA_RX_CH_MAP Register 1364 ................14-129. P0_RX_DSCP_PRI_MAP0 Register 1365 ................14-130. P0_RX_DSCP_PRI_MAP1 Register 1366 SPRUH73H – October 2011 – Revised April 2013 List of Figures Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 34 ....................14-176. SOFT_RESET Register 1417 ....................14-177. RX_MAXLEN Register 1418 ....................14-178. BOFFTEST Register 1419 ....................14-179. RX_PAUSE Register 1420 List of Figures SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 35 ....................14-225. C0_RX_IMAX Register 1467 ....................14-226. C0_TX_IMAX Register 1468 ....................14-227. C1_RX_IMAX Register 1469 ....................14-228. C1_TX_IMAX Register 1470 SPRUH73H – October 2011 – Revised April 2013 List of Figures Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 36 15-28. Up, Single Edge Asymmetric Waveform With Independent Modulation on EPWMxA and ....................EPWMxB—Active Low 1524 ..15-29. Up-Count, Pulse Placement Asymmetric Waveform With Independent Modulation on EPWMxA 1526 List of Figures SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 37 15-73. Time-Base Counter Register (TBCNT) 1585 ................15-74. Time-Base Period Register (TBPRD) 1586 ..............15-75. Counter-Compare Control Register (CMPCTL) 1587 SPRUH73H – October 2011 – Revised April 2013 List of Figures Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 38 ......................15-121. CAP4 Register 1640 ..................... 15-122. ECCTL1 Register 1641 ..................... 15-123. ECCTL2 Register 1643 ...................... 15-124. ECEINT Register 1645 List of Figures SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 39 15-171. eQEP Capture Timer Latch Register (QCTMRLAT) 1688 ............. 15-172. eQEP Capture Period Latch Register (QCPRDLAT) 1689 ................15-173. eQEP Revision ID Register (REVID) 1689 SPRUH73H – October 2011 – Revised April 2013 List of Figures Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 40 ................... 16-46. IRQFRAMETHOLDTX00 Register 1786 ................... 16-47. IRQFRAMETHOLDTX01 Register 1787 ................... 16-48. IRQFRAMETHOLDTX02 Register 1788 ................... 16-49. IRQFRAMETHOLDTX03 Register 1789 List of Figures SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 41 ....................16-95. USB0_TDOWN Register 1850 ....................16-96. USB0UTMI Register 1851 ..................16-97. USB0MGCUTMILB Register 1852 ....................16-98. USB0MODE Register 1853 SPRUH73H – October 2011 – Revised April 2013 List of Figures Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 42 ....................16-144. CDR_BIST2 Register 1916 ......................16-145. GPIO Register 1917 ....................... 16-146. DLLHS Register 1918 ................... 16-147. USB2PHYCM_CONFIG Register 1919 List of Figures SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 43 ....................16-193. RXHPCRA9 Register 1980 ....................16-194. RXHPCRB9 Register 1981 ....................16-195. TXGCR10 Register 1982 ....................16-196. RXGCR10 Register 1983 SPRUH73H – October 2011 – Revised April 2013 List of Figures Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 44 ....................16-242. RXHPCRB21 Register 2041 ....................16-243. TXGCR22 Register 2042 ....................16-244. RXGCR22 Register 2043 ....................16-245. RXHPCRA22 Register 2045 List of Figures SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 45 ....................... 16-291. PEND1 Register 2123 ....................... 16-292. PEND2 Register 2124 ....................... 16-293. PEND3 Register 2125 ....................... 16-294. PEND4 Register 2126 SPRUH73H – October 2011 – Revised April 2013 List of Figures Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 46 ....................16-340. QUEUE_7_B Register 2172 ....................16-341. QUEUE_7_C Register 2173 ....................16-342. QUEUE_7_D Register 2174 ....................16-343. QUEUE_8_A Register 2175 List of Figures SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 47 ....................16-389. QUEUE_19_C Register 2221 ....................16-390. QUEUE_19_D Register 2222 ....................16-391. QUEUE_20_A Register 2223 ....................16-392. QUEUE_20_B Register 2224 SPRUH73H – October 2011 – Revised April 2013 List of Figures Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 48 ....................16-438. QUEUE_31_D Register 2270 ....................16-439. QUEUE_32_A Register 2271 ....................16-440. QUEUE_32_B Register 2272 ....................16-441. QUEUE_32_C Register 2273 List of Figures SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 49 ....................16-487. QUEUE_44_A Register 2319 ....................16-488. QUEUE_44_B Register 2320 ....................16-489. QUEUE_44_C Register 2321 ....................16-490. QUEUE_44_D Register 2322 SPRUH73H – October 2011 – Revised April 2013 List of Figures Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 50 ....................16-536. QUEUE_56_B Register 2368 ....................16-537. QUEUE_56_C Register 2369 ....................16-538. QUEUE_56_D Register 2370 ....................16-539. QUEUE_57_A Register 2371 List of Figures SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 51 ....................16-585. QUEUE_68_C Register 2417 ....................16-586. QUEUE_68_D Register 2418 ....................16-587. QUEUE_69_A Register 2419 ....................16-588. QUEUE_69_B Register 2420 SPRUH73H – October 2011 – Revised April 2013 List of Figures Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 52 ....................16-634. QUEUE_80_D Register 2466 ....................16-635. QUEUE_81_A Register 2467 ....................16-636. QUEUE_81_B Register 2468 ....................16-637. QUEUE_81_C Register 2469 List of Figures SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 53 ....................16-683. QUEUE_93_A Register 2515 ....................16-684. QUEUE_93_B Register 2516 ....................16-685. QUEUE_93_C Register 2517 ....................16-686. QUEUE_93_D Register 2518 SPRUH73H – October 2011 – Revised April 2013 List of Figures Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 54 ..................... 16-732. QUEUE_105_B Register 2564 ..................... 16-733. QUEUE_105_C Register 2565 ..................... 16-734. QUEUE_105_D Register 2566 ..................... 16-735. QUEUE_106_A Register 2567 List of Figures SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 55 ..................... 16-781. QUEUE_117_C Register 2613 ..................... 16-782. QUEUE_117_D Register 2614 ..................... 16-783. QUEUE_118_A Register 2615 ..................... 16-784. QUEUE_118_B Register 2616 SPRUH73H – October 2011 – Revised April 2013 List of Figures Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 56 ..................... 16-830. QUEUE_129_D Register 2662 ..................... 16-831. QUEUE_130_A Register 2663 ..................... 16-832. QUEUE_130_B Register 2664 ..................... 16-833. QUEUE_130_C Register 2665 List of Figures SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 57 ..................... 16-879. QUEUE_142_A Register 2711 ..................... 16-880. QUEUE_142_B Register 2712 ..................... 16-881. QUEUE_142_C Register 2713 ..................... 16-882. QUEUE_142_D Register 2714 SPRUH73H – October 2011 – Revised April 2013 List of Figures Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 58 ..................... 16-928. QUEUE_154_B Register 2760 ..................... 16-929. QUEUE_154_C Register 2761 ..................... 16-930. QUEUE_154_D Register 2762 ..................... 16-931. QUEUE_155_A Register 2763 List of Figures SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 59 .................. 16-977. QUEUE_14_STATUS_A Register 2809 .................. 16-978. QUEUE_14_STATUS_B Register 2810 .................. 16-979. QUEUE_14_STATUS_C Register 2811 .................. 16-980. QUEUE_15_STATUS_A Register 2812 SPRUH73H – October 2011 – Revised April 2013 List of Figures Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 60 ................. 16-1026. QUEUE_30_STATUS_B Register 2858 ................. 16-1027. QUEUE_30_STATUS_C Register 2859 ................. 16-1028. QUEUE_31_STATUS_A Register 2860 ................. 16-1029. QUEUE_31_STATUS_B Register 2861 List of Figures SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 61 ................. 16-1075. QUEUE_46_STATUS_C Register 2907 ................. 16-1076. QUEUE_47_STATUS_A Register 2908 ................. 16-1077. QUEUE_47_STATUS_B Register 2909 ................. 16-1078. QUEUE_47_STATUS_C Register 2910 SPRUH73H – October 2011 – Revised April 2013 List of Figures Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 62 ................. 16-1124. QUEUE_63_STATUS_A Register 2956 ................. 16-1125. QUEUE_63_STATUS_B Register 2957 ................. 16-1126. QUEUE_63_STATUS_C Register 2958 ................. 16-1127. QUEUE_64_STATUS_A Register 2959 List of Figures SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 63 ................. 16-1173. QUEUE_79_STATUS_B Register 3005 ................. 16-1174. QUEUE_79_STATUS_C Register 3006 ................. 16-1175. QUEUE_80_STATUS_A Register 3007 ................. 16-1176. QUEUE_80_STATUS_B Register 3008 SPRUH73H – October 2011 – Revised April 2013 List of Figures Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 64 ................. 16-1222. QUEUE_95_STATUS_C Register 3054 ................. 16-1223. QUEUE_96_STATUS_A Register 3055 ................. 16-1224. QUEUE_96_STATUS_B Register 3056 ................. 16-1225. QUEUE_96_STATUS_C Register 3057 List of Figures SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 65 ................16-1271. QUEUE_112_STATUS_A Register 3103 ................16-1272. QUEUE_112_STATUS_B Register 3104 ................16-1273. QUEUE_112_STATUS_C Register 3105 ................16-1274. QUEUE_113_STATUS_A Register 3106 SPRUH73H – October 2011 – Revised April 2013 List of Figures Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 66 ................16-1320. QUEUE_128_STATUS_B Register 3152 ................16-1321. QUEUE_128_STATUS_C Register 3153 ................16-1322. QUEUE_129_STATUS_A Register 3154 ................16-1323. QUEUE_129_STATUS_B Register 3155 List of Figures SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 67 ................16-1369. QUEUE_144_STATUS_C Register 3201 ................16-1370. QUEUE_145_STATUS_A Register 3202 ................16-1371. QUEUE_145_STATUS_B Register 3203 ................16-1372. QUEUE_145_STATUS_C Register 3204 SPRUH73H – October 2011 – Revised April 2013 List of Figures Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 68 ..................... 17-16. FIFOSTATUS_3 Register 3261 ..................... 17-17. FIFOSTATUS_4 Register 3262 ..................... 17-18. FIFOSTATUS_5 Register 3263 ..................... 17-19. FIFOSTATUS_6 Register 3264 List of Figures SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 69 ....................17-65. LOCK_REG_17 Register 3329 ....................17-66. LOCK_REG_18 Register 3330 ....................17-67. LOCK_REG_19 Register 3331 ....................17-68. LOCK_REG_20 Register 3332 SPRUH73H – October 2011 – Revised April 2013 List of Figures Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 70 18-36. MMC/SD/SDIO Controller Card Identification and Selection - Part 2 3388 .................... 18-37. SD_SYSCONFIG Register 3390 .................... 18-38. SD_SYSSTATUS Register 3392 List of Figures SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 71 19-19. SIR Free Format Mode 3483 ..................19-20. MIR Transmit Frame Format 3483 ................19-21. MIR BAUD Rate Adjustment Mechanism 3484 SPRUH73H – October 2011 – Revised April 2013 List of Figures Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 72 19-68. Divisor Latches Low Register (DLL) 3536 ................19-69. Divisor Latches High Register (DLH) 3536 ................... 19-70. Enhanced Feature Register (EFR) 3537 List of Figures SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 73 20-32. Timing Diagram of Pulse-Width Modulation, SCPWM Bit = 0 3594 ............ 20-33. Timing Diagram of Pulse-Width Modulation, SCPWM Bit = 1 3594 SPRUH73H – October 2011 – Revised April 2013 List of Figures Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 74 ..................... 20-79. RTC_OSC_REG Register 3653 ..................20-80. RTC_SCRATCH0_REG Register 3654 ..................20-81. RTC_SCRATCH1_REG Register 3655 ..................20-82. RTC_SCRATCH2_REG Register 3656 List of Figures SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 75 ............21-15. Transmit FIFO DMA Request Generation (Low Threshold) 3712 ..................... 21-16. I2C_REVNB_LO Register 3717 ....................21-17. I2C_REVNB_HI Register 3718 SPRUH73H – October 2011 – Revised April 2013 List of Figures Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 76 22-18. Receive Clock Generator Block Diagram 3785 ................22-19. Frame Sync Generator Block Diagram 3786 ....................22-20. Burst Frame Sync Mode 3788 List of Figures SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 77 22-67. Transmit Clock Control Register (ACLKXCTL) 3866 ..........22-68. Transmit High-Frequency Clock Control Register (AHCLKXCTL) 3867 ................. 22-69. Transmit TDM Time Slot Register (XTDM) 3868 SPRUH73H – October 2011 – Revised April 2013 List of Figures Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 78 ....................... 23-30. TXRQ56 Register 3938 ....................... 23-31. TXRQ78 Register 3939 ....................23-32. NWDAT_X Register 3940 ....................23-33. NWDAT12 Register 3941 List of Figures SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 79 24-7. Full Duplex Single Transfer Format with PHA = 0 4002 ..............24-8. Full Duplex Single Transfer Format With PHA = 1 4003 SPRUH73H – October 2011 – Revised April 2013 List of Figures Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 80 ................25-14. GPIO_IRQSTATUS_SET_0 Register 4076 ................25-15. GPIO_IRQSTATUS_SET_1 Register 4077 ................25-16. GPIO_IRQSTATUS_CLR_0 Register 4078 ................25-17. GPIO_IRQSTATUS_CLR_1 Register 4079 List of Figures SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 81 26-26. Image Formats on GP Devices 4150 ..................... 26-27. Wakeup Booting by ROM 4153 .................... 27-1. Suspend Control Registers 4158 SPRUH73H – October 2011 – Revised April 2013 List of Figures Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 82 6-29. INTC_PENDING_IRQ1 Register Field Descriptions ..............6-30. INTC_PENDING_FIQ1 Register Field Descriptions ................6-31. INTC_ITR2 Register Field Descriptions ................6-32. INTC_MIR2 Register Field Descriptions List of Tables SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 83 7-31. Enable Chip-Select ....................7-32. NAND Memory Type ..................7-33. NAND Chip-Select Configuration ................7-34. Asynchronous Read and Write Operations SPRUH73H – October 2011 – Revised April 2013 List of Tables Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 84 ................. 7-80. GPMC_ECC_CONTROL Field Descriptions ..............7-81. GPMC_ECC_SIZE_CONFIG Field Descriptions ................7-82. GPMC_ECCj_RESULT Field Descriptions ................ 7-83. GPMC_BCH_RESULT0_i Field Descriptions List of Tables SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 85 7-124. PWR_MGMT_CTRL_SHDW Register Field Descriptions ..............7-125. Interface Configuration Register Field Descriptions ............7-126. Interface Configuration Value 1 Register Field Descriptions SPRUH73H – October 2011 – Revised April 2013 List of Tables Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 86 7-162. DDR PHY Data Macro 0/1 Delay Selection Register (DATA0/1_REG_PHY_USE_RANK0_DELAYS) ......................Field Descriptions .................... 7-163. ELM Connectivity Attributes ....................... 7-164. ELM Clock Signals ................... 7-165. Local Power Management Features List of Tables SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 87 8-21. PLL and Clock Frequences ................. 8-22. Core PLL Typical Frequencies (MHz) ..................... 8-23. Bus Interface Clocks .................. 8-24. Per PLL Typical Frequencies (MHz) SPRUH73H – October 2011 – Revised April 2013 List of Tables Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 88 8-70. CM_PER_L3_INSTR_CLKCTRL Register Field Descriptions ............... 8-71. CM_PER_L3_CLKCTRL Register Field Descriptions ............8-72. CM_PER_IEEE5000_CLKCTRL Register Field Descriptions ............ 8-73. CM_PER_PRU_ICSS_CLKCTRL Register Field Descriptions List of Tables SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 89 8-119. CM_AUTOIDLE_DPLL_PER Register Field Descriptions .............. 8-120. CM_IDLEST_DPLL_PER Register Field Descriptions ..........8-121. CM_SSC_DELTAMSTEP_DPLL_PER Register Field Descriptions ..........8-122. CM_SSC_MODFREQDIV_DPLL_PER Register Field Descriptions SPRUH73H – October 2011 – Revised April 2013 List of Tables Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 90 8-168. CM_RTC_CLKSTCTRL Register Field Descriptions ....................8-169. CM_GFX REGISTERS ............8-170. CM_GFX_L3_CLKSTCTRL Register Field Descriptions ............8-171. CM_GFX_GFX_CLKCTRL Register Field Descriptions List of Tables SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 91 ................9-1. Pad Control Register Field Descriptions ......................9-2. Mode Selection ......................9-3. Pull Selection .................... 9-4. Interconnect Priority Values SPRUH73H – October 2011 – Revised April 2013 List of Tables Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 92 9-50. mpuss_hw_debug_sel Register Field Descriptions ..............9-51. mpuss_hw_dbg_info Register Field Descriptions ..............9-52. vdd_mpu_opp_050 Register Field Descriptions ..............9-53. vdd_mpu_opp_100 Register Field Descriptions List of Tables SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 93 9-99. ddr_cmd1_ioctrl Register Field Descriptions ................. 9-100. ddr_cmd2_ioctrl Register Field Descriptions ................. 9-101. ddr_data0_ioctrl Register Field Descriptions ................. 9-102. ddr_data1_ioctrl Register Field Descriptions SPRUH73H – October 2011 – Revised April 2013 List of Tables Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 94 11-45. QDMA Region Access Enable for Region M (QRAEm) Field Descriptions ............11-46. Event Queue Entry Registers (QxEy) Field Descriptions ............11-47. Queue Status Register n (QSTATn) Field Descriptions List of Tables SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 95 11-94. Error Register (ERRSTAT) Field Descriptions ..............11-95. Error Enable Register (ERREN) Field Descriptions 1000 ..............11-96. Error Clear Register (ERRCLR) Field Descriptions 1001 SPRUH73H – October 2011 – Revised April 2013 List of Tables Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 96 12-25. STEPCONFIG2 Register Field Descriptions 1059 ................. 12-26. STEPDELAY2 Register Field Descriptions 1060 ................ 12-27. STEPCONFIG3 Register Field Descriptions 1061 List of Tables SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 97 13-12. Highlander 0.8 Interrupt Module Control Registers 1119 ...................... 13-13. LCD REGISTERS 1128 ..................13-14. PID Register Field Descriptions 1130 SPRUH73H – October 2011 – Revised April 2013 List of Tables Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 98 14-21. Values of messageType field 1232 .................... 14-22. MDIO Read Frame Format 1233 .................... 14-23. MDIO Write Frame Format 1233 List of Tables SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 99 14-70. DMA_INTSTAT_MASKED Register Field Descriptions 1290 ..............14-71. DMA_INTMASK_SET Register Field Descriptions 1291 ............. 14-72. DMA_INTMASK_CLEAR Register Field Descriptions 1292 SPRUH73H – October 2011 – Revised April 2013 List of Tables Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 100 14-119. TX0_CP Register Field Descriptions 1340 ................14-120. TX1_CP Register Field Descriptions 1341 ................14-121. TX2_CP Register Field Descriptions 1342 List of Tables SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 101 14-168. P1_RX_DSCP_PRI_MAP6 Register Field Descriptions 1390 ............14-169. P1_RX_DSCP_PRI_MAP7 Register Field Descriptions 1391 ............... 14-170. P2_CONTROL Register Field Descriptions 1392 SPRUH73H – October 2011 – Revised April 2013 List of Tables Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 102 14-217. CONTROL Register Field Descriptions 1441 ..............14-218. INT_CONTROL Register Field Descriptions 1442 ............... 14-219. C0_RX_THRESH_EN Register Field Descriptions 1443 List of Tables SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 103 14-263. MDIO User Access Register 1 (MDIOUSERACCESS1) Field Descriptions 1483 ......14-264. MDIO User PHY Select Register 1 (MDIOUSERPHYSEL1) Field Descriptions 1484 SPRUH73H – October 2011 – Revised April 2013 List of Tables Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 104 15-46. EPWM1 Initialization for 1564 ....................15-47. EPWM2 Initialization for 1564 ....................15-48. EPWM1 Initialization for 1567 ....................15-49. EPWM2 Initialization for 1567 List of Tables SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 105 15-97. ECAP Initialization for CAP Mode Absolute Time, Rising and Falling Edge Trigger 1622 ..........15-98. ECAP Initialization for CAP Mode Delta Time, Rising Edge Trigger 1624 SPRUH73H – October 2011 – Revised April 2013 List of Tables Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 106 15-146. eQEP Capture Timer Latch Register (QCTMRLAT) Field Descriptions 1688 ........15-147. eQEP Capture Period Latch Register (QCPRDLAT) Field Descriptions 1689 List of Tables SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 107 16-46. IRQDMATHOLDTX12 Register Field Descriptions 1778 ..............16-47. IRQDMATHOLDTX13 Register Field Descriptions 1779 ..............16-48. IRQDMATHOLDRX10 Register Field Descriptions 1780 SPRUH73H – October 2011 – Revised April 2013 List of Tables Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 108 16-95. USB0GENRNDISEP9 Register Field Descriptions 1840 ............... 16-96. USB0GENRNDISEP10 Register Field Descriptions 1841 ............... 16-97. USB0GENRNDISEP11 Register Field Descriptions 1842 List of Tables SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 109 1901 ....................16-144. USB2PHY REGISTERS 1901 ..............16-145. Termination_control Register Field Descriptions 1903 ................16-146. RX_CALIB Register Field Descriptions 1904 SPRUH73H – October 2011 – Revised April 2013 List of Tables Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 110 16-193. RXHPCRA6 Register Field Descriptions 1965 ................16-194. RXHPCRB6 Register Field Descriptions 1966 ................16-195. TXGCR7 Register Field Descriptions 1967 List of Tables SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 111 16-242. RXHPCRB18 Register Field Descriptions 2026 ................16-243. TXGCR19 Register Field Descriptions 2027 ................16-244. RXGCR19 Register Field Descriptions 2028 SPRUH73H – October 2011 – Revised April 2013 List of Tables Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 112 16-291. QMGRREVID Register Field Descriptions 2109 ................16-292. QMGRRST Register Field Descriptions 2110 ................16-293. FDBSC0 Register Field Descriptions 2111 List of Tables SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 113 16-340. QUEUE_3_D Register Field Descriptions 2158 ................16-341. QUEUE_4_A Register Field Descriptions 2159 ................16-342. QUEUE_4_B Register Field Descriptions 2160 SPRUH73H – October 2011 – Revised April 2013 List of Tables Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 114 16-389. QUEUE_16_A Register Field Descriptions 2207 ................ 16-390. QUEUE_16_B Register Field Descriptions 2208 ................ 16-391. QUEUE_16_C Register Field Descriptions 2209 List of Tables SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 115 16-438. QUEUE_28_B Register Field Descriptions 2256 ................ 16-439. QUEUE_28_C Register Field Descriptions 2257 ................ 16-440. QUEUE_28_D Register Field Descriptions 2258 SPRUH73H – October 2011 – Revised April 2013 List of Tables Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 116 16-487. QUEUE_40_C Register Field Descriptions 2305 ................ 16-488. QUEUE_40_D Register Field Descriptions 2306 ................ 16-489. QUEUE_41_A Register Field Descriptions 2307 List of Tables SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 117 16-536. QUEUE_52_D Register Field Descriptions 2354 ................ 16-537. QUEUE_53_A Register Field Descriptions 2355 ................ 16-538. QUEUE_53_B Register Field Descriptions 2356 SPRUH73H – October 2011 – Revised April 2013 List of Tables Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 118 16-585. QUEUE_65_A Register Field Descriptions 2403 ................ 16-586. QUEUE_65_B Register Field Descriptions 2404 ................ 16-587. QUEUE_65_C Register Field Descriptions 2405 List of Tables SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 119 16-634. QUEUE_77_B Register Field Descriptions 2452 ................ 16-635. QUEUE_77_C Register Field Descriptions 2453 ................ 16-636. QUEUE_77_D Register Field Descriptions 2454 SPRUH73H – October 2011 – Revised April 2013 List of Tables Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 120 16-683. QUEUE_89_C Register Field Descriptions 2501 ................ 16-684. QUEUE_89_D Register Field Descriptions 2502 ................ 16-685. QUEUE_90_A Register Field Descriptions 2503 List of Tables SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 121 16-732. QUEUE_101_D Register Field Descriptions 2550 ............... 16-733. QUEUE_102_A Register Field Descriptions 2551 ............... 16-734. QUEUE_102_B Register Field Descriptions 2552 SPRUH73H – October 2011 – Revised April 2013 List of Tables Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 122 16-781. QUEUE_114_A Register Field Descriptions 2599 ............... 16-782. QUEUE_114_B Register Field Descriptions 2600 ..............16-783. QUEUE_114_C Register Field Descriptions 2601 List of Tables SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 123 16-830. QUEUE_126_B Register Field Descriptions 2648 ..............16-831. QUEUE_126_C Register Field Descriptions 2649 ..............16-832. QUEUE_126_D Register Field Descriptions 2650 SPRUH73H – October 2011 – Revised April 2013 List of Tables Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 124 16-879. QUEUE_138_C Register Field Descriptions 2697 ..............16-880. QUEUE_138_D Register Field Descriptions 2698 ............... 16-881. QUEUE_139_A Register Field Descriptions 2699 List of Tables SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 125 16-928. QUEUE_150_D Register Field Descriptions 2746 ............... 16-929. QUEUE_151_A Register Field Descriptions 2747 ............... 16-930. QUEUE_151_B Register Field Descriptions 2748 SPRUH73H – October 2011 – Revised April 2013 List of Tables Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 126 16-977. QUEUE_9_STATUS_B Register Field Descriptions 2795 ............. 16-978. QUEUE_9_STATUS_C Register Field Descriptions 2796 ............16-979. QUEUE_10_STATUS_A Register Field Descriptions 2797 List of Tables SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 127 16-1026. QUEUE_25_STATUS_C Register Field Descriptions 2844 ............16-1027. QUEUE_26_STATUS_A Register Field Descriptions 2845 ............16-1028. QUEUE_26_STATUS_B Register Field Descriptions 2846 SPRUH73H – October 2011 – Revised April 2013 List of Tables Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 128 16-1075. QUEUE_42_STATUS_A Register Field Descriptions 2893 ............16-1076. QUEUE_42_STATUS_B Register Field Descriptions 2894 ............16-1077. QUEUE_42_STATUS_C Register Field Descriptions 2895 List of Tables SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 129 16-1124. QUEUE_58_STATUS_B Register Field Descriptions 2942 ............16-1125. QUEUE_58_STATUS_C Register Field Descriptions 2943 ............16-1126. QUEUE_59_STATUS_A Register Field Descriptions 2944 SPRUH73H – October 2011 – Revised April 2013 List of Tables Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 130 16-1173. QUEUE_74_STATUS_C Register Field Descriptions 2991 ............16-1174. QUEUE_75_STATUS_A Register Field Descriptions 2992 ............16-1175. QUEUE_75_STATUS_B Register Field Descriptions 2993 List of Tables SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 131 16-1222. QUEUE_91_STATUS_A Register Field Descriptions 3040 ............16-1223. QUEUE_91_STATUS_B Register Field Descriptions 3041 ............16-1224. QUEUE_91_STATUS_C Register Field Descriptions 3042 SPRUH73H – October 2011 – Revised April 2013 List of Tables Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 132 16-1271. QUEUE_107_STATUS_B Register Field Descriptions 3089 ............16-1272. QUEUE_107_STATUS_C Register Field Descriptions 3090 ............16-1273. QUEUE_108_STATUS_A Register Field Descriptions 3091 List of Tables SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 133 16-1320. QUEUE_123_STATUS_C Register Field Descriptions 3138 ............16-1321. QUEUE_124_STATUS_A Register Field Descriptions 3139 ............16-1322. QUEUE_124_STATUS_B Register Field Descriptions 3140 SPRUH73H – October 2011 – Revised April 2013 List of Tables Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 134 16-1369. QUEUE_140_STATUS_A Register Field Descriptions 3187 ............16-1370. QUEUE_140_STATUS_B Register Field Descriptions 3188 ............16-1371. QUEUE_140_STATUS_C Register Field Descriptions 3189 List of Tables SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 135 17-1. Mailbox Connectivity Attributes 3237 ....................17-2. Mailbox Clock Signals 3238 ....................17-3. Mailbox Implementation 3238 ................. 17-4. Local Power Management Features 3239 SPRUH73H – October 2011 – Revised April 2013 List of Tables Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 136 17-51. IRQENABLE_SET_2 Register Field Descriptions 3294 ..............17-52. IRQENABLE_CLR_2 Register Field Descriptions 3296 ..............17-53. IRQSTATUS_RAW_3 Register Field Descriptions 3298 List of Tables SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 137 3351 .................... 18-8. Response Type Summary 3355 ................. 18-9. Local Power Management Features 3360 ....................18-10. Clock Activity Settings 3360 SPRUH73H – October 2011 – Revised April 2013 List of Tables Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 138 19-8. UART Pin List 3452 ....................19-9. UART Muxing Control 3452 ................. 19-10. Local Power-Management Features 3456 ....................19-11. UART Mode Interrupts 3456 List of Tables SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 139 19-58. Supplementary Control Register (SCR) Field Descriptions 3529 ............19-59. Supplementary Status Register (SSR) Field Descriptions 3530 ..............19-60. BOF Length Register (EBLR) Field Descriptions 3531 SPRUH73H – October 2011 – Revised April 2013 List of Tables Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 140 20-22. TTGR Register Field Descriptions 3579 ................... 20-23. TWPS Register Field Descriptions 3580 ................... 20-24. TMAR Register Field Descriptions 3581 List of Tables SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 141 20-71. ALARM_SECONDS_REG Register Field Descriptions 3641 ............. 20-72. ALARM_MINUTES_REG Register Field Descriptions 3642 ............... 20-73. ALARM_HOURS_REG Register Field Descriptions 3643 SPRUH73H – October 2011 – Revised April 2013 List of Tables Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 142 20-120. WDT_WTGR Register Field Descriptions 3690 ................. 20-121. WDT_WWPS Register Field Descriptions 3691 ................20-122. WDT_WDLY Register Field Descriptions 3692 List of Tables SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 143 22-2. McASP Clock Signals 3772 ......................22-3. McASP Pin List 3772 ....................22-4. Biphase-Mark Encoder 3779 ......................22-5. Preamble Codes 3780 SPRUH73H – October 2011 – Revised April 2013 List of Tables Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 144 22-52. Read FIFO Status Register (RFIFOSTS) Field Descriptions 3880 ..............22-53. McASP Registers Accessed Through Data Port 3880 ..................23-1. DCAN Connectivity Attributes 3883 List of Tables SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 145 23-48. IF1ARB Register Field Descriptions 3963 ................23-49. IF1MCTL Register Field Descriptions 3964 ................23-50. IF1DATA Register Field Descriptions 3966 SPRUH73H – October 2011 – Revised April 2013 List of Tables Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 146 25-1. GPIO0 Connectivity Attributes 4059 ..................25-2. GPIO[1:3] Connectivity Attributes 4059 ....................25-3. GPIO Clock Signals 4059 ......................25-4. GPIO Pin List 4060 List of Tables SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 147 ..................26-20. Configuration Header TOC Item 4132 ..................26-21. Configuration Header Settings 4132 ..................26-22. Master Boot Record Structure 4134 SPRUH73H – October 2011 – Revised April 2013 List of Tables Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 148 ..................27-1. Debug Subsystem Registers 4157 ..............27-2. Suspend Control Registers Field Descriptions 4158 ................... A-1. Document Revision History 4159 List of Tables SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 149 USSE is a trademark of Imagination Technologies Ltd.. POWERVR is a registered trademark of Imagination Technologies Ltd.. EtherNet/IP is a trademark of Open DeviceNet Vendor Association, Inc.. SPRUH73H – October 2011 – Revised April 2013 Read This First Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 150: Device Features
ZCZ: 2 ports ZCZ: 2 ports ZCZ: 2 ports ZCZ: 2 ports Interprocessor Communication Multimedia Card (MMC) Universal Asynchronous Receiver/Transmitter (UART) DMTimer 150 Introduction SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 151: Device_Id (Address 0X44E10600) Bit Field Descriptions
AM335x family. See Table 1-3, dev_feature Register, in the control module chapter for more information on the bits in the DEV_FEATURE register. SPRUH73H – October 2011 – Revised April 2013 Introduction Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 152: Dev_Feature (Address 0X44E10604) Register Values
Table 1-3. DEV_FEATURE (Address 0x44E10604) Register Values Register Value Reserved Reserved Reserved Definition AM3352 0x00FC0382 AM3354 0x20FC0382 AM3356 0x00FD0383 AM3357 0x00FF0383 AM3358 0x20FD0383 AM3359 0x20FF0383 152 Introduction SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 153 6.3, ARM Cortex-A8 Interrupts and Errata Advisory 1.0.6. PG1.0: nNMI input signal is active high. PG2.x: nNMI input signal is active low. SPRUH73H – October 2011 – Revised April 2013 Introduction Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 154 PG1.0: EFUSE_SMA register value is not applicable. Value is always 0. PG2.x: Added EFUSE_SMA description to distinguish package type and maximum ARM frequency of the device. Introduction SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 155: L3 Memory Map
Reserved 0x4680_0000 0x46FF_FFFF Reserved Reserved 0x4700_0000 0x473F_FFFF Reserved The first 1MB of address space 0x0-0xFFFFF is inaccessible externally. Ex/R/W – Execute/Read/Write. SPRUH73H – October 2011 – Revised April 2013 Memory Map Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 156 Reserved 0x5700_0000 0x57FF_FFFF 16MB Reserved Reserved 0x5800_0000 0x58FF_FFFF 16MB Reserved Reserved 0x5900_0000 0x59FF_FFFF 16MB Reserved Reserved 0x5A00_0000 0x5AFF_FFFF 16MB Reserved 156 Memory Map SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 157: L4_Wkup Peripheral Memory Map
Power Reset Module Graphics Controller Registers PRM_CEFUSE 0x44E0_1200 0x44E0_12FF 256 Bytes Power Reset Module Efuse Registers Reserved 0x44E0_3000 0x44E0_3FFF Reserved 0x44E0_4000 0x44E0_4FFF Reserved SPRUH73H – October 2011 – Revised April 2013 Memory Map Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 158: L4_Per Peripheral Memory Map
0x4800_4000 0x4800_7FFF 16KB Reserved Reserved 0x4800_8000 0x4800_8FFF Reserved 0x4800_9000 0x4800_9FFF Reserved Reserved 0x4800_A000 0x4800_FFFF 24KB Reserved Reserved 0x4801_0000 0x4801_0FFF Reserved 158 Memory Map SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 159 L4 Interconnect DMTIMER7 0x4804_A000 0x4804_AFFF DMTimer7 Registers 0x4804_B000 0x4804_BFFF Reserved GPIO1 0x4804_C000 0x4804_CFFF GPIO1 Registers 0x4804_D000 0x4804_DFFF Reserved Reserved 0x4804_E000 0x4804_FFFF Reserved SPRUH73H – October 2011 – Revised April 2013 Memory Map Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 160 Reserved 0x4819_2000 0x4819_2FFF Reserved 0x4819_3000 0x4819_3FFF Reserved Reserved 0x4819_4000 0x4819_BFFF 32KB Reserved I2C2 0x4819_C000 0x4819_CFFF I2C2 Registers 0x4819_D000 0x4819_DFFF Reserved 160 Memory Map SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 161 0x4830_0100 0x4830_017F PWMSS eCAP0 Registers eQEP0 0x4830_0180 0x4830_01FF PWMSS eQEP0 Registers ePWM0 0x4830_0200 0x4830_025F PWMSS ePWM0 Registers 0x4830_0260 0x4830_1FFF Reserved SPRUH73H – October 2011 – Revised April 2013 Memory Map Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 162: L4 Fast Peripheral Memory Map
CPSW_SL1 0x4A10_0D80 0x4A10_0DBF Ethernet Sliver for Port 1 CPSW_SL2 0x4A10_0DC0 0x4A10_0DFF Ethernet Sliver for Port 2 Reserved 0x4A10_0E00 0x4A10_0FFF Reserved 162 Memory Map SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 163 Reserved PRU_ICSS 0x4A30_0000 0x4A37_FFFF 512KB PRU-ICSS Instruction/Data/Control Space 0x4A38_0000 0x4A38_0FFF Reserved Reserved 0x4A38_1000 0x4A3F_FFFF 508KB Reserved Reserved 0x4A40_0000 0x4AFF_FFFF 12MB Reserved SPRUH73H – October 2011 – Revised April 2013 Memory Map Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 164 ARM MPU Subsystem This chapter describes the MPU Subsystem for the device..........................Topic Page ............... ARM Cortex-A8 MPU Subsystem ARM MPU Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 165: Microprocessor Unit (Mpu) Subsystem
OCP Master 0 OCP Master 1 CLK_M_OSC T2ASYNC T2ASYNC Frm Master OSC 200 MHz 200 MHz To L3 To L3 SPRUH73H – October 2011 – Revised April 2013 ARM MPU Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 166 SYSCLK2 which is fed by the power, reset, and clock management (PRCM) module of the device. In-Circuit Emulator: It is fully Compatible with CoreSight Architecture and enables debugging capabilities. ARM MPU Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 167: Microprocessor Unit (Mpu) Subsystem Signal Interface
The MPU subsystem includes an embedded DPLL which sources the clock for the ARM Cortex-A8 processor. A clock divider within the subsystem is used for deriving the clocks for other internal modules. SPRUH73H – October 2011 – Revised April 2013 ARM MPU Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 168: Mpu Subsystem Clocking Scheme
AXI2OCP Bridge Functional Clock MPU_CLK / 2 Device Clock MPU_CLK / 2 I2Async Bridge Functional Clock MPU_CLK / 2 168 ARM MPU Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 169: Reset Scheme Of The Mpu Subsystem
Table 3-2. Reset Scheme of the MPU Subsystem Signal Name Interface MPU_RST PRCM NEON_RST PRCM CORE_RST PRCM MPU_RSTPWRON PRCM EMU_RST PRCM EMU_RSTPWRON PRCM SPRUH73H – October 2011 – Revised April 2013 ARM MPU Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 170 ; secure monitor call SMC (previously SMI) LDMFD sp!, {r0 - r4} ; after returning from SMC, restore R0-R4 MOV pc, lr ; return ARM MPU Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 171: Arm Core Supported Features
Power Domains The MPU subsystem is divided into 5 power domains controlled by the PRCM, as shown in Figure Figure 3-5. SPRUH73H – October 2011 – Revised April 2013 ARM MPU Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 172: Mpu Subsystem Power Domain Overview
ICE-Crusher, ETM, APB modules MPU NEON domain ARM NEON accelerator CORE domain MPU interrupt controller EMU domain EMU (ETB,DAP) ARM MPU Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 173: Mpu Power States
The MPU subsystem must be in a power mode where the MPU power domain, NEON power domain, debug power domain, and INTC power domain are in standby, or off state. SPRUH73H – October 2011 – Revised April 2013 ARM MPU Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 174: Mpu Subsystem Operation Power Modes
NOTE: The INTC SWAKEUP output is a pure hardware signal to PRCM for the status of its IDLE request and IDLE acknowledge handshake. ARM MPU Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 175 NOTE: The core domain must be on, and reset, before the MPU can be reset. 2. Follow the reset sequence as described in the Basic Power-On Reset section. SPRUH73H – October 2011 – Revised April 2013 ARM MPU Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 176 Communication Subsystem (PRU-ICSS) This chapter describes the PRU-ICSS for the device..........................Topic Page ....................Introduction Programmable Real-Time Unit and Industrial Communication Subsystem SPRUH73H – October 2011 – Revised April 2013 (PRU-ICSS) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 177 NOTE: For the availability of EtherCAT in the AM335x family of devices, see Table 1-1, Device Features. SPRUH73H – October 2011 – Revised April 2013 Programmable Real-Time Unit and Industrial Communication Subsystem (PRU-ICSS) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 178 Graphics Accelerator (SGX) This chapter describes the graphics accelerator for the device..........................Topic Page ....................Introduction ...................... Integration ..................Functional Description Graphics Accelerator (SGX) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 179 Introduction www.ti.com Introduction This chapter describes the 2D/3D graphics accelerator (SGX) for the device. NOTE: The SGX subsystem is a Texas Instruments instantiation of the POWERVR SGX530 core ® from Imagination Technologies Ltd. This document contains materials that are ©2003-2007 Imagination Technologies Ltd.
Page 180 – Effective geometry compression – High-order surface support • External data access: – Permits reads from main memory using cache Graphics Accelerator (SGX) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 181 – Data fence facility – Dependent texture reads 5.1.4 Unsupported Features There are no unsupported SGX530 features for this device. SPRUH73H – October 2011 – Revised April 2013 Graphics Accelerator (SGX) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 182: Sgx530 Integration
200 MHz CORE_CLKOUTM4 pd_gfx_gfx_l3_gclk Memory Clock From PRCM CORECLK 200 MHz PER_CLKOUTM2 or pd_gfx_gfx_fclk Functional clock CORE_CLKOUTM4 From PRCM 182 Graphics Accelerator (SGX) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 183 Integration www.ti.com 5.2.3 SGX530 Pin List The SGX530 module does not include any external interface pins. SPRUH73H – October 2011 – Revised April 2013 Graphics Accelerator (SGX) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 184: Sgx Block Diagram
There are three data masters in the SGX core: • The VDM is the initiator of transform and lighting processing within the system. The VDM reads an Graphics Accelerator (SGX) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 185 The address order is determined by the frame buffer mode. The pixel coprocessor contains a dithering and packing function. SPRUH73H – October 2011 – Revised April 2013 Graphics Accelerator (SGX) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 186 This section describes the interrupts for the device..........................Topic Page ..................Functional Description ................Basic Programming Model ................. ARM Cortex-A8 Interrupts ....................PWM Events ................Interrupt Controller Registers Interrupts SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 187: Interrupt Controller Block Diagram
Priority Sorting Spurious Flag Control and Priority NEWFIQAGR SIR_FIQ NEWIRQAGR Priority Sorter FIQ_PRIORITY Priority Sorter SIR_IRQ IRQ_PRIORITY IRQ Input FIQ Input Processor SPRUH73H – October 2011 – Revised April 2013 Interrupts Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 188 INTC restarts the appropriate priority sorter; otherwise, the IRQ or FIQ interrupt line is deasserted. Interrupts SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 189 MPU_INTC.INTC_SIR_IRQ or MPU_INTC.INTC_SIR_FIQ register is read. SPRUH73H – October 2011 – Revised April 2013 Interrupts Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 190 /* Disable FIQ */ if high vectors configured then PC = 0xFFFF001C else PC = 0x0000001C /* execute interrupt vector */ endif Interrupts SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 191 The code in steps 5 and 7 is an assembly code compatible with ARM architecture V6 and V7. This code is developed for the Texas Instruments Code Composer Studio tool set. It is a draft version, only tested on an emulated environment.
Page 192 It is sorted when the NEWIRQAGR/NEWFIQAGR bit is set (priority sorting is reactivated). Interrupts SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 193: Irq/Fiq Processing Sequence
ARM Host Processor (Step 8) Restore ARM critical context. Return Restore the whole CPSR Main Program Restore the PC Execution of instruction number N + 1 SPRUH73H – October 2011 – Revised April 2013 Interrupts Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 194 IRQs/FIQs, a Data Synchronization Barrier is used. This operation ensure that the IRQ line is de-asserted before IRQ/FIQ enabling. 7. Enable IRQ/FIQ at ARM side. 8. Jump to the relevant subroutine handler. Interrupts SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 195 CAUTION The following code is an assembly code compatible with ARM architecture V6 and V7. This code is developed for the Texas Instruments Code Composer Studio tool set. It is a draft version, only tested on an emulated environment. ; bit field mask to get only the bit field ACTIVEPRIO_MASK .equ 0x7F...
Page 196 CAUTION The following code is an assembly code compatible with ARM architecture V6 and V7. This code is developed for the Texas Instruments Code Composer Studio tool set. It is a draft version, only tested on an emulated environment. IRQ_ISR_end: ;...
Page 197: Nested Irq/Fiq Processing Sequence
ARM Host Processor (Step 8) Restore ARM critical context. Restore the whole CPSR Return Main Program Restore the PC Execution of instruction number N + 1 SPRUH73H – October 2011 – Revised April 2013 Interrupts Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 198 The INTC_SIR_IRQ[31:7] SPURIOUSIRQFLAG bit field is a copy of the INTC_IRQ_PRIORITY[31:7] SPURIOUSIRQFLAG bit field. The INTC_SIR_FIQ[31:7] SPURIOUSFIQFLAG bit field is a copy of the INTC_FIQ_PRIORITY[31:7] SPURIOUSFIQFLAG bit field. Interrupts SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 199: Arm Cortex-A8 Interrupts
For differences in operation based on AM335x silicon revisions, see Section 1.2, Silicon Revision Functional Differences and Enhancements. pr1_host_intr[0:7] corresponds to Host-2 to Host-9 of the PRU-ICSS interrupt controller. SPRUH73H – October 2011 – Revised April 2013 Interrupts Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 200 RTCINT timer_intr_pend RTCALARMINT alarm_intr_pend MBINT0 Mailbox0 (mail_u0_irq) initiator_sinterrupt_q_n0 M3_TXEV Wake M3 Subsystem TXEV eQEP0INT eQEP0 (PWM Subsystem) eqep_intr_intr_pend MCATXINT0 McASP0 mcasp_x_intr_pend 200 Interrupts SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 201 SMRFLX_Core Smart Reflex 1 intrpend Reserved DMA_INTR_PIN0 External DMA/Interrupt Pin0 pi_x_dma_event_intr0 (xdma_event_intr0) DMA_INTR_PIN1 External DMA/Interrupt Pin1 pi_x_dma_event_intr1 (xdma_event_intr1) McSPI1INT McSPI1 SINTERRUPTN SPRUH73H – October 2011 – Revised April 2013 Interrupts Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 202 ARM Cortex-A8 Interrupts www.ti.com Table 6-1. ARM Cortex-A8 Interrupts (continued) Int Number Acronym/name Source Signal Name Reserved Reserved Interrupts SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 203: Timer And Ecap Event Capture
GPIOINT2A GPIO 2 GPIOINT2B GPIO 3 GPIOINT3A GPIO 3 GPIOINT3B DCAN0 DCAN0_INT0 DCAN0 DCAN0_INT1 DCAN0 DCAN0_PARITY DCAN1 DCAN1_INT0 DCAN1 DCAN1_INT1 DCAN1 DCAN1_PARITY SPRUH73H – October 2011 – Revised April 2013 Interrupts Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 204: Intc Registers
INTC_ISR_CLEAR2 Section 6.5.1.33 INTC_PENDING_IRQ2 Section 6.5.1.34 INTC_PENDING_FIQ2 Section 6.5.1.35 INTC_ITR3 Section 6.5.1.36 INTC_MIR3 Section 6.5.1.37 INTC_MIR_CLEAR3 Section 6.5.1.38 INTC_MIR_SET3 Section 6.5.1.39 204 Interrupts SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 205 Register Name Section INTC_ISR_SET3 Section 6.5.1.40 INTC_ISR_CLEAR3 Section 6.5.1.41 INTC_PENDING_IRQ3 Section 6.5.1.42 INTC_PENDING_FIQ3 Section 6.5.1.43 100h to INTC_ILR0 to INTC_ILR127 Section 6.5.1.44 2FCh SPRUH73H – October 2011 – Revised April 2013 Interrupts Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 206: Intc_Revision Register
Reset Description 31-8 Reserved Reads returns 0 IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 1.0, 0x21 for 2.1 Interrupts SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 207: Intc_Sysconfig Register
0x0 = clkfree : OCP clock is free running 0x1 = autoClkGate : Automatic OCP clock gating strategy is applied, bnased on the OCP interface activity SPRUH73H – October 2011 – Revised April 2013 Interrupts Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 208: Intc_Sysstatus Register
Reserved for OCP socket status information Read returns 0 ResetDone Internal reset monitoring 0x0 = rstOngoing : Internal module reset is on-going 0x1 = rstComp : Reset completed Interrupts SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 209: Intc_Sir_Irq Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 6-7. INTC_SIR_IRQ Register Field Descriptions Field Type Reset Description 31-7 SpuriousIRQ 1FFFFFFh Spurious IRQ flag ActiveIRQ Active IRQ number SPRUH73H – October 2011 – Revised April 2013 Interrupts Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 210: Intc_Sir_Fiq Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 6-8. INTC_SIR_FIQ Register Field Descriptions Field Type Reset Description 31-7 SpuriousFIQ 1FFFFFFh Spurious FIQ flag ActiveFIQ Active FIQ number Interrupts SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 211: Intc_Control Register
0x1(Write) = NewFiq_Reset FIQ output and enable new FIQ generation NewIRQAgr New IRQ generation 0x0(Write) = nofun_no function effect 0x1(Write) = NewIrq_Reset IRQ output and enable new IRQ generation SPRUH73H – October 2011 – Revised April 2013 Interrupts Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 212: Intc_Protection Register
0x0 = ProtMDis : Protection mode disabled (default) 0x1 = ProtMEnb : Protection mode enabled. When enabled, only priviledged mode can access registers. Interrupts SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 213: Intc_Idle Register
Functional clock auto-idle mode 0x0 = FuncAuto : Functional clock gating strategy is applied (default) 0x1 = FuncFree : Functional clock is free-running SPRUH73H – October 2011 – Revised April 2013 Interrupts Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 214: Intc_Irq_Priority Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 6-12. INTC_IRQ_PRIORITY Register Field Descriptions Field Type Reset Description 31-7 SpuriousIRQflag 1FFFFFFh Spurious IRQ flag IRQPriority Current IRQ priority Interrupts SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 215: Intc_Fiq_Priority Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 6-13. INTC_FIQ_PRIORITY Register Field Descriptions Field Type Reset Description 31-7 SpuriousFIQflag 1FFFFFFh Spurious FIQ flag FIQPriority Current FIQ priority SPRUH73H – October 2011 – Revised April 2013 Interrupts Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 216: Intc_Threshold Register
Type Reset Description 31-8 Reserved Reads returns 0 PriorityThreshold Priority threshold (used values 0x 00-0x1f or 0x 00-0x3f, 0xff disables the threshold). Interrupts SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 217: Intc_Itr0 Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 6-15. INTC_ITR0 Register Field Descriptions Field Type Reset Description 31-0 Interrupt status before masking SPRUH73H – October 2011 – Revised April 2013 Interrupts Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 218: Intc_Mir0 Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 6-16. INTC_MIR0 Register Field Descriptions Field Type Reset Description 31-0 FFFFFFFFh Interrupt mask Interrupts SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 219: Intc_Mir_Clear0 Register
Table 6-17. INTC_MIR_CLEAR0 Register Field Descriptions Field Type Reset Description 31-0 MirClear Write 1 clears the mask bit to 0, reads return 0 SPRUH73H – October 2011 – Revised April 2013 Interrupts Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 220: Intc_Mir_Set0 Register
Table 6-18. INTC_MIR_SET0 Register Field Descriptions Field Type Reset Description 31-0 MirSet Write 1 sets the mask bit to 1, reads return 0 Interrupts SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 221: Intc_Isr_Set0 Register
Field Type Reset Description 31-0 IsrSet Reads returns the currently active software interrupts, Write 1 sets the software interrupt bits to 1 SPRUH73H – October 2011 – Revised April 2013 Interrupts Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 222: Intc_Isr_Clear0 Register
Table 6-20. INTC_ISR_CLEAR0 Register Field Descriptions Field Type Reset Description 31-0 IsrClear Write 1 clears the sofware interrupt bits to 0, reads return 0 Interrupts SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 223: Intc_Pending_Irq0 Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 6-21. INTC_PENDING_IRQ0 Register Field Descriptions Field Type Reset Description 31-0 PendingIRQ IRQ status after masking SPRUH73H – October 2011 – Revised April 2013 Interrupts Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 224: Intc_Pending_Fiq0 Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 6-22. INTC_PENDING_FIQ0 Register Field Descriptions Field Type Reset Description 31-0 PendingFIQ FIQ status after masking Interrupts SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 225: Intc_Itr1 Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 6-23. INTC_ITR1 Register Field Descriptions Field Type Reset Description 31-0 Interrupt status before masking SPRUH73H – October 2011 – Revised April 2013 Interrupts Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 226: Intc_Mir1 Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 6-24. INTC_MIR1 Register Field Descriptions Field Type Reset Description 31-0 FFFFFFFFh Interrupt mask Interrupts SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 227: Intc_Mir_Clear1 Register
Table 6-25. INTC_MIR_CLEAR1 Register Field Descriptions Field Type Reset Description 31-0 MirClear Write 1 clears the mask bit to 0, reads return 0 SPRUH73H – October 2011 – Revised April 2013 Interrupts Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 228: Intc_Mir_Set1 Register
Table 6-26. INTC_MIR_SET1 Register Field Descriptions Field Type Reset Description 31-0 MirSet Write 1 sets the mask bit to 1, reads return 0 Interrupts SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 229: Intc_Isr_Set1 Register
Field Type Reset Description 31-0 IsrSet Reads returns the currently active software interrupts, Write 1 sets the software interrupt bits to 1 SPRUH73H – October 2011 – Revised April 2013 Interrupts Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 230: Intc_Isr_Clear1 Register
Table 6-28. INTC_ISR_CLEAR1 Register Field Descriptions Field Type Reset Description 31-0 IsrClear Write 1 clears the sofware interrupt bits to 0, reads return 0 Interrupts SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 231: Intc_Pending_Irq1 Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 6-29. INTC_PENDING_IRQ1 Register Field Descriptions Field Type Reset Description 31-0 PendingIRQ IRQ status after masking SPRUH73H – October 2011 – Revised April 2013 Interrupts Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 232: Intc_Pending_Fiq1 Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 6-30. INTC_PENDING_FIQ1 Register Field Descriptions Field Type Reset Description 31-0 PendingFIQ FIQ status after masking Interrupts SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 233: Intc_Itr2 Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 6-31. INTC_ITR2 Register Field Descriptions Field Type Reset Description 31-0 Interrupt status before masking SPRUH73H – October 2011 – Revised April 2013 Interrupts Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 234: Intc_Mir2 Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 6-32. INTC_MIR2 Register Field Descriptions Field Type Reset Description 31-0 FFFFFFFFh Interrupt mask Interrupts SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 235: Intc_Mir_Clear2 Register
Table 6-33. INTC_MIR_CLEAR2 Register Field Descriptions Field Type Reset Description 31-0 MirClear Write 1 clears the mask bit to 0, reads return 0 SPRUH73H – October 2011 – Revised April 2013 Interrupts Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 236: Intc_Mir_Set2 Register
Table 6-34. INTC_MIR_SET2 Register Field Descriptions Field Type Reset Description 31-0 MirSet Write 1 sets the mask bit to 1, reads return 0 Interrupts SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 237: Intc_Isr_Set2 Register
Field Type Reset Description 31-0 IsrSet Reads returns the currently active software interrupts, Write 1 sets the software interrupt bits to 1 SPRUH73H – October 2011 – Revised April 2013 Interrupts Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 238: Intc_Isr_Clear2 Register
Table 6-36. INTC_ISR_CLEAR2 Register Field Descriptions Field Type Reset Description 31-0 IsrClear Write 1 clears the sofware interrupt bits to 0, reads return 0 Interrupts SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 239: Intc_Pending_Irq2 Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 6-37. INTC_PENDING_IRQ2 Register Field Descriptions Field Type Reset Description 31-0 PendingIRQ IRQ status after masking SPRUH73H – October 2011 – Revised April 2013 Interrupts Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 240: Intc_Pending_Fiq2 Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 6-38. INTC_PENDING_FIQ2 Register Field Descriptions Field Type Reset Description 31-0 PendingFIQ FIQ status after masking Interrupts SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 241: Intc_Itr3 Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 6-39. INTC_ITR3 Register Field Descriptions Field Type Reset Description 31-0 Interrupt status before masking SPRUH73H – October 2011 – Revised April 2013 Interrupts Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 242: Intc_Mir3 Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 6-40. INTC_MIR3 Register Field Descriptions Field Type Reset Description 31-0 FFFFFFFFh Interrupt mask Interrupts SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 243: Intc_Mir_Clear3 Register
Table 6-41. INTC_MIR_CLEAR3 Register Field Descriptions Field Type Reset Description 31-0 MirClear Write 1 clears the mask bit to 0, reads return 0 SPRUH73H – October 2011 – Revised April 2013 Interrupts Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 244: Intc_Mir_Set3 Register
Table 6-42. INTC_MIR_SET3 Register Field Descriptions Field Type Reset Description 31-0 MirSet Write 1 sets the mask bit to 1, reads return 0 Interrupts SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 245: Intc_Isr_Set3 Register
Field Type Reset Description 31-0 IsrSet Reads returns the currently active software interrupts, Write 1 sets the software interrupt bits to 1 SPRUH73H – October 2011 – Revised April 2013 Interrupts Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 246: Intc_Isr_Clear3 Register
Table 6-44. INTC_ISR_CLEAR3 Register Field Descriptions Field Type Reset Description 31-0 IsrClear Write 1 clears the sofware interrupt bits to 0, reads return 0 Interrupts SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 247: Intc_Pending_Irq3 Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 6-45. INTC_PENDING_IRQ3 Register Field Descriptions Field Type Reset Description 31-0 PendingIRQ IRQ status after masking SPRUH73H – October 2011 – Revised April 2013 Interrupts Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 248: Intc_Pending_Fiq3 Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 6-46. INTC_PENDING_FIQ3 Register Field Descriptions Field Type Reset Description 31-0 PendingFIQ FIQ status after masking Interrupts SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 249: Intc_Ilr0 To Intc_Ilr127 Register
0x0 = IntIRQ : Interrupt is routed to IRQ. 0x1 = IntFIQ : Interrupt is routed to FIQ (this selection is reserved on GP devices). SPRUH73H – October 2011 – Revised April 2013 Interrupts Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 250 Memory Subsystem This chapter describes the memory subsystem of the device..........................Topic Page ......................GPMC ..................... OCMC-RAM ....................... EMIF ....................... Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 251 Flexible internal access time control (wait state) and flexible handshake mode using external WAIT pins monitoring (up to two WAIT pins) • Support bus keeping • Support bus turn around SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 252 Address decoder, GPMC configuration, and chip-select configuration register file • Access engine • Prefetch and write-posting engine • Error correction code engine (ECC) • External device/memory port interface Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 253: Gpmc Block Diagram
Not pinned out 32-bit devices Only 16 data lines pinned out WAIT[3:2] Not pinned out. All CS regions must use WAIT0 or WAIT1 SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 254: Gpmc Integration
Clock Signal Max Freq Reference / Source Comments prcm_gpmc_clk 100 MHz CORE_CLKOUTM4 / 2 pd_per_l3s_gclk Interface / Functional clock From PRCM 254 Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 255: Gpmc Signal List
1 to enable the clock input back to the module. It is also recommended to place a 33-ohm resistor in series (close to the processor) to avoid signal reflections. SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 256: Gpmc Pin Multiplexing Options
Some label the LSB as A0, while others use A1 for the LSB. These columns assume the LSB is A0. 256 Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 257 Multiplexing mode can be selected through the GPMC_CONFIG1_i[9-8] MUXADDDATA bit field. • Asynchronous page mode is not supported for multiplexed address and data devices. SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 258: Gpmc To 16-Bit Address/Data-Multiplexed Memory
A[16:1]/D[15:0] A/D[15:0] gpmc_csn[6:0] CSn[6:0] gpmc_advn_ale ADVn_ALE ADVn gpmc_oen OEn_REn gpmc_wen gpmc_be0n_cle BE0n_CLE BE0n/CLE gpmc_be1n BE1n BE1n gpmc_wpn gpmc_wait[1:0] WAIT[1:0] WAIT gpmc_clk Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 259: Gpmc To 16-Bit Non-Multiplexed Memory
D[7:0] D[7:0] gpmc_csn[6:0] CSn[6:0] gpmc_advn_ale ADVn_ALE ADVn/ALE gpmc_oen OEn_REn OEn/REn gpmc_wen BE0n_CLE gpmc_be0n_cle gpmc_be1n BE1n gpmc_wpn gpmc_wait[1:0] WAIT[1:0] WAIT gpmc_clk SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 260 Most GPMC external interface control-signal assertion and deassertion times • Data-capture time during read access • External wait-pin monitoring time • Duration of idle time between accesses, when required Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 261: Gpmc_Config1_I
Feature not available Master Standby Modes Feature not available Global Wake-up Enable Feature not available Wake-up Sources Enable Feature not available SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 262: Gpmc Interrupt Events
Bursts larger than the memory page length are chopped into multiple bursts transactions. Due to the alignment requirements, a page boundary is never crossed. Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 263 After the chip-select is configured, the access engine accesses the external device, drives the external interface control signals, and applies the interface protocol based on user-defined timing parameters and settings. SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 264: Chip-Select Address Mapping And Decoding Mask
Also, the write buffer state must be monitored to wait for any posted write completion to the chip-select. Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 265 They also allow the overlap of wait-pin assertion from different devices without affecting access to devices for which the wait pin is not asserted. SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 266 GPMCFCLKDIVIDER is used as a divider for the GPMC clock, so it must be programmed to define the correct WAITMONITORINGTIME delay. Figure 7-7 shows wait behavior during an asynchronous single read access. Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 267: Wait Behavior During An Asynchronous Single Read Access (Gpmcfclkdivider = 1)
All signals, including the data bus, are controlled according to their related control timing value and to the CYCLETIME counter status. SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 268 CYCLETIME counter status. Figure 7-8 shows wait behavior during a synchronous read burst access. Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 269: Wait Behavior During A Synchronous Read Burst Access
At WRACCESSTIME completion if WAITMONITORINGTIME = 0 • In the WAITMONITORINGTIME x (GPMCFCLKDIVIDER + 1) GPMC_FCLK cycles before WRACCESSTIME completion if WAITMONITORINGTIME not equal to 0. SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 270 RDCYCLETIME. Doing this prevents bus contention, but affects all accesses of this specific chip-select. Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 271: Read To Read For An Address-Data Multiplexed Device, On Different Cs, Without Bus Turnaround (Cs0N Attached To Fast Device)
Figure 7-10. Read to Read / Write for an Address-Data Multiplexed Device, On Different CS, With Bus Turnaround A[16:1]/D[15:0] DATA 0 ADD 1 OEOFFTIME RDCYCLETIME RD/WRCYCLETIME CSOFFTIME nCS0 BUSTURNAROUND nCS1 SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 272: Read To Read / Write For A Address-Data Or Aad-Multiplexed Device, On Same Cs, With Bus Turnaround
CYCLE2CYCLEDELAY inactive cycles is inserted between the access being initiated to this chip-select and the previous access ending for a different chip-select. This applies to any type of access (read or write). Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 273: Idle Cycle Insertion Configuration
If BTA idle cycles already apply on these two back-to-back >0 Different accesses, the effective delay is maximum (BUSTURNAROUND, CYCLE2CYCLEDELAY). SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 274 GPMC_ERR_TYPE register is reset. Subsequent accesses that cause errors are not logged until the error is cleared by hardware with the GPMC_ERR_TYPE[0]ERRORVALID bit. Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 275: Gpmc_Timeout_Control
The GPMC_CONFIG2_i[3-0] CSONTIME field defines the CSn signal-assertion time relative to the start access time. It is common for read and write accesses. SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 276 ADVONTIME, ADVRDOFFTIME, ADVWROFFTIME, and ADVAADMUXRDOFFTIME, ADVAADMUXWROFFTIME usage for CLE and ALE (Command / Address Latch Enable) usage for a NAND Flash interface. Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 277 This implies the need to program the WRCYCLETIME bit field to be greater than the WEn signal-deassertion time, including the extra half-GPMC_FCLK-period delay. SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 278 GPMC_FCLK cycles from start access time to the GPMC_FCLK rising edge corresponding to the GPMC_CLK rising edge used for the first data capture. Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 279 After a write access, if no other access is pending, the GPMC keeps driving the data bus after WRCYCLETIME completes with the same data to prevent bus floating and power consumption. SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 280 Asynchronous multiple (page) read operation on a non-multiplexed device In asynchronous operations GPMC_CLK is not provided outside the GPMC and is kept low. Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 281: Asynchronous Single Read Operation On An Address/Data Multiplexed Device
– ADVn assertion time is controlled by the GPMC_CONFIG3_i[3-0] ADVONTIME field. – ADVn deassertion time is controlled by the GPMC_CONFIG3_i[[12-8] ADVRDOFFTIME field. SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 282: Two Asynchronous Single Read Accesses On An Address/Data Multiplexed Device (32-Bit Read Split Into 2 × 16-Bit Read)
Valid address 1 Data 1 Data 1 nBE1/nBE0 CSRDOFFTIME CSRDOFFTIME CSONTIME CSONTIME ADVRDOFFTIME ADVRDOFFTIME ADVONTIME ADVONTIME nADV OEOFFTIME OEOFFTIME OEONTIME OEONTIME WAIT Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 283: Asynchronous Single Write On An Address/Data-Multiplexed Device
Write multiple access in asynchronous mode is not supported. If WRITEMULTIPLE is enabled with WRITETYPE as asynchronous, the GPMC processes single asynchronous accesses. SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 284: Asynchronous Single-Read On An Aad-Multiplexed Device
Data 0 Data 0 A[16:1]/D[15:0] MSB Address LSB Add nBE1/nBE0 CSRDOFFTIME CSONTIME ADVRDOFFTIME ADVONTIME ADVAADMUXRDOFFTIME ADVAADMUXONTIME nADV OEOFFTIME OEONTIME OEAADMUXOFFTIME OEAADMUXONTIME WAIT Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 285 – OEn second assertion time is controlled by the GPMC_CONFIG4_i[3-0] OEONTIME field. – OEn second deassertion time is controlled by the GPMC_CONFIG4_i[12-8] OEOFFTIME field. SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 286: Asynchronous Single Write On An Aad-Multiplexed Device
Valid Address WRDATAONADMUXBUS A[16:1]/D[15:0] MSB Address LSB Address Data nBE1/nBE0 CSWROFFTIME CSONTIME ADVWROFFTIME ADVONTIME ADVAADMUXWROFFTIME ADVAADMUXONTIME nADV OEAADMUXOFFTIME OEAADMUXONTIME WEOFFTIME WEONTIME WAIT Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 287 The GPMC_CONFIG1_i[26-25] CLKACTIVATIONTIME field specifies that the GPMC_CLK is provided outside the GPMC 0, 1, or 2 GPMC_FCLK cycles after start access time until RDCYCLETIME or WRCYCLETIME completion. SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 288: Synchronous Single Read (Gpmcfclkdivider = 0)
RDCYCLETIME RDACCESSTIME GPMC_FCLK CLKACTIVATIONTIME GPMC_CLK A[27:17] Valid Address WRDATAONADMUXBUS A[16:1]/D[15:0] Valid Address nBE1/nBE0 CSRDOFFTIME CSONTIME ADVRDOFFTIME ADVONTIME nADV OEOFFTIME OEONTIME WAIT Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 289: Synchronous Single Read (Gpmcfclkdivider = 1)
Total access time (GPMC_CONFIG5_i[4-0] RDCYCLETIME) corresponds to RDACCESSTIME plus the address hold time from CSn deassertion, plus time from RDACCESSTIME to CSRDOFFTIME. SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 290 After a read operation, if no other access (read or write) is pending, the data bus is driven with the previous read value. See Section 7.1.3.3.9.10. Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 291: Synchronous Multiple (Burst) Read (Gpmcfclkdivider = 0)
CLKACTIVATIONTIME GPMC_FCLK GPMC_CLK A[27:17] Valid Address A[16:1]/D[15:0] Valid Address D1 D2 nBE1/nBE0 CSRDOFFTIME0 CSRDOFFTIME1 CSONTIME ADVRDOFFTIME ADVONTIME nADV OEOFFTIME OEONTIME WAIT SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 292: Synchronous Multiple (Burst) Read (Gpmcfclkdivider = 1)
Burst wraparound is enabled through the GPMC_CONFIG1_i[31] WRAPBURST bit and allows a 4-, 8-, or 16-Word16 linear burst access to wrap within its burst-length boundary through GPMC_CONFIG1_i[24-23] ATTACHEDDEVICEPAGELENGTH. Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 293: Synchronous Single Write On An Address/Data-Multiplexed Device
(with address bits A[16:1]) until [19:16] WRDATAONADMUXBUS time. First data of the burst is driven on the address/data bus at WRDATAONADMUXBUS time. SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 294: Synchronous Multiple Write (Burst Write) In Address/Data-Multiplexed Mode
WEOFFTIME WEONTIME WAIT Figure 7-23 shows the same synchronous burst write access when the chip-select is configured in address/address/data-multiplexed (AAD-multiplexed) mode. Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 295: Synchronous Multiple Write (Burst Write) In Address/Address/Data-Multiplexed Mode
– ADVn assertion time is controlled by the GPMC_CONFIG3_i[3-0] ADVONTIME field. – ADVn deassertion time is controlled by the GPMC_CONFIG3_i[20-16] ADVWROFFTIME field. SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 296 Asynchronous single write operation on a nonmultiplexed device • Asynchronous multiple (page mode) read operation on a nonmultiplexed device • Synchronous operations on a nonmultiplexed device Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 297: Asynchronous Single Read On An Address/Data-Nonmultiplexed Device
GPMC_CONFIG1_5[4-0] RDCYCLETIME parameter. CSn, ADVn, OEn and DIR signals are controlled in the same way as address/data multiplexed accesses, Section 7.1.3.3.10.1.1.2. SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 298: Asynchronous Single Write On An Address/Data-Nonmultiplexed Device
The 27-bit address is driven onto the address bus A[27:1] and the 16-bit data is driven onto the data bus D[15:0]. CSn, ADVn, WEn and DIR signals are controlled in the same way as address/data multiplexed accesses, Section 7.1.3.3.10.1.1.3. Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 299: Asynchronous Multiple (Page Mode) Read
The read cycle time is defined in the GPMC_CONFIG5_i[4-0] RDCYCLETIME field. • Figure 7-26, the RDCYCLETIME programmed value equals RDCYCLETIME0 (before paged accesses) + RDCYCLETIME1 (after paged accesses). SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 300 (4 or 8) are also supported, assuming that the GPMC_CONFIG1_i[24-23] ATTACHEDDEVICEPAGELENGTH field is set accordingly to 4 or 8 words. Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 301 NAND device data read and write accesses are achieved through an asynchronous read or write access. The associated chip-select signal timing control must be programmed according to the NAND device timing specification. SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 302: Chip-Select Configuration For Nand Interfacing
These locations are mapped in the associated chip-select register region. The associated chip-select signal timing control must be programmed according to the NAND device timing specification. Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 303 MSByte of the 16-bit word value must be set according to the NAND device requirement (usually 0). Either 16-bit word location or any one of the four byte locations of the registers is valid SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 304: Nand Command Latch Cycle
NAND Flash memories do not use byte enable signals at all. Figure 7-27. NAND Command Latch Cycle WRCYCLETIME CSWROFFTIME CSONTIME = 0 nBE0/CLE WEOFFTIME WEONTIME = 0 nADV/ALE D[15:0] Command Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 305: Nand Address Latch Cycle
WRCYCLETIME CSWROFFTIME = WRCYCLETIME CSONTIME = 0 nBE0/CLE WEOFFTIME WEONTIME = 0 ADVWROFFTIME = WRCYCLETIME ADVONTIME = 0 nADV/ALE D[15:0] Address SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 306: Nand Data Read Cycle
WEn is controlled by the WEONTIME and WEOFFTIME timing parameters. • ALE, CLE, and REn (OEn) are maintained inactive. Figure 7-30 shows the NAND data write cycle. Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 307: Nand Data Write Cycle
16-bit word accesses to the NAND memory device. 16-bit word access is ordered according to little-endian organization. SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 308 Depending on whether the GPMC_CONFIG WAITxPINPOLARITY bits (x = 0 or 1) is active low or active high, the wait-to-no-wait transition is a low-to-high external WAIT signal transition or a high-to-low external WAIT signal transition, respectively. Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 309 NAND flash memory while the ECC computation engine is active. SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 310: Gpmc_Ecc_Config
The ECC accumulator and ECC result register must not be changed or cleared while an ECC computation is in progress. Table 7-12 describes the ECC enable settings. Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 311: Hamming Code Accumulation Algorithm (1 Of 2)
Row 255 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit5 bit3 bit1 SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 312: Hamming Code Accumulation Algorithm (2 Of 2)
P16o Row 255 Row 255 bit7 bit7 bit6 bit6 bit5 bit5 bit4 bit4 bit3 bit3 bit2 bit2 bit1 bit1 bit0 bit0 Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 313: Ecc Computation For A 512-Byte Data Stream (Read Or Write)
(LSB) of the 16-bit wide data is ordered first in the byte stream used for 8- bit based ECC computation. SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 314: Word16 Ecc Computation
P16o P16o Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 315 ECC may or may not be protected by the same ECC scheme, by extending the BCH message beyond 512 bytes (maximum codeword is 1023-byte long, ECC included, which leaves a lot of space to cover some spares bytes). SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 316: Flattened Bch Codeword Mapping (512 Bytes + 104 Bits)
Table 7-14. Aligned Message Byte Mapping in 8-bit NAND Byte Offset 8-Bit Word (msb) Byte 511 (1FFh) Byte 510 (1FEh) ⋮ ⋮ 1FFh Byte 0 (0) (LSB) Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 317: Aligned Message Byte Mapping In 16-Bit Nand
S/2 - 4 Nibble 5 Nibble 4 Nibble 7 Nibble 6 S/2 - 2 Nibble 1 Nibble 0 (LSB) Nibble 3 Nibble 2 SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 318: Misaligned Nibble Mapping Of Message In 16-Bit Nand (1 Unused Nibble)
(concatenated message and remainder) once an error as been detected. The creation of this codeword should be made as straightforward as possible. Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 319: Manual Mode Sequence And Mapping
Manual mode to ECC divider unused Protected data Unused data Mode Size 0 Size 1 Rd/Wr/ bch_blk_ptr inactive size 0 size1 SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 320 Repeat with buffer 0 to S-1 – size1 nibbles spare, processing ON Checksum: Spare area size (nibbles) = size0 + (S - size1) Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 321 – 1 nibble padding spare, processing OFF – size1 nibbles spare, processing ON Checksum: Spare area size (nibbles) = size0 + (S - (1+size1)) SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 322 Repeat S times (no buffer used) – size1 nibbles spare, processing OFF Checksum: Spare area size (nibbles) = S - (size0 + size1) Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 323 – sector 0 codeword: (512) + P + E – other sectors: (512) + E • Unprotected spares (Figure 7-38: see M4-M7-M8-M11-M12): – all codewords (512) + E SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 324: Nand Page Mapping And Ecc: Per-Sector Schemes
Ecc0 Unprot1 Ecc1 Mode Size0 Size1 512 bytes 512 bytes Write inactive size0 size0 Read inactive inactive size0 size1 size0 size1 Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 325: Nand Page Mapping And Ecc: Pooled Spare Schemes
Unprotected (pooled) Ecc0 Ecc1 Mode Size0 Size1 512 bytes 512 bytes Write inactive +1+E size1 size1 Read inactive size1 size0 size1 SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 326: Nand Page Mapping And Ecc: Per-Sector Schemes, With Separate Ecc
Unprot0 Unprot1 Ecc0 Ecc1 Mode Size0 Size1 512 bytes 512 bytes Write U+1+E inactive size1 size1 Read inactive size0 size1 size1 Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 327 (the address bus is not changed from its current value). Selecting a different chip-select configuration can produce undefined behavior. SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 328 In write-posting mode, when the FIFOPOINTER equals 0, that is, the FIFO is full, a host write overwrites the last FIFO byte location. There is no underflow or overflow error reporting in the GPMC. Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 329: Gpmc_Prefetch_Config1
Section 7.1.3.3.12.4.6 CYCLEOPTIMIZATION GPMC_PREFETCH_CONFIG1 Number of clock cycle removed to timing parameters ENABLEENGINE GPMC_PREFETCH_CONFIG1 Engine enabled STARTENGINE GPMC_PREFETCH_CONFIG1 Starts the prefetch engine SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 330 (the STARTENGINE bit is set to 1). The associated DMA channel must always be enabled by the MPU after setting the STARTENGINE bit so that the out-of-date active DMA request does not trigger spurious DMA transfers. Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 331: Write-Posting Mode Configuration
Engine starts the access to chip-select as soon as STARTENGINE is set. ENABLEOPTIMIZEDACCESS GPMC_PREFETCH_CONFIG1 Section 7.1.3.3.12.4.6 CYCLEOPTIMIZATION GPMC_PREFETCH_CONFIG ENABLEENGINE GPMC_PREFETCH_CONFIG1 Engine enabled STARTENGINE GPMC_PREFETCH_CONTROL Starts the prefetch engine SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 332: Gpmc_Prefetch_Status
In write-posting mode, the DMA or the MPU fill the FIFO with no consideration to the associated byte enables. Any byte stored in the FIFO is written into the memory device. Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 333: Nand Read Cycle Optimization Timing Description
OEOFFTIME − x clk cycles nOE/nRE nADV/ALE D[15:0] Data 0 Data 1 WAIT x is the programmed value in the GPMC_PREFETCH_CONFIG1[30:28] CYCLEOPTIMIZATION field SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 334 The GPMC then grants priority to the engine for three requests, and finnaly back to the direct interconnect access, until the arbiter is reset when one of the two initiators stops initiating requests. Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 335 Table 7-24 Table 7-25 list each step in the model. SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 336: Programming Model Top-Level Diagram
10. ECC engine * 11. Prefetch and write posting engine * 12. Wait pin configuration * 13. Enable chip-select * Optional Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 337: Gpmc Configuration In Nor Mode
GPMC. Table 7-26. Reset GPMC Sub-process Name Register / Bitfield Value Start a software reset GPMC_SYSCONFIG[1] SOFTRESET Wait until GPMC_SYSSTATUS[0] RESETDONE SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 338: Wait Pin Configuration
GPMC_CONFIG1_i[21] WAITWRITEMONITORING GPMC_CONFIG1_i[19-18] Select a wait pin monitoring time WAITMONITORINGTIME Choose the input wait pin for the chip-select GPMC_CONFIG1_i[17-16] WAITPINSELECT 338 Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 339: Enable Chip-Select
If the BCH code is used, GPMC_ECC_SIZE_CONFIG[13-12] ECCBCHTSEL Set an error correction capability and and GPMC_ECC_SIZE_CONFIG[6-4] Select a number of sectors to process ECCTOPSECTOR SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 340 GPMC www.ti.com Table 7-35. ECC Engine (continued) Sub-process Name Register / Bitfield Value Enable the ECC computation GPMC_ECC_SIZE_CONFIG[0] ECCENABLE 340 Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 341: Wait Pin Configuration
WAITPINSELECTOR Table 7-38. Enable Chip-Select Sub-process Name Register / Bitfield Value When all parameters are configured, enable the chip-select GPMC_CONFIG7_i[6] CSVALID SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 342: Mode Parameters Check List Table
Table 7-40. Access Type Parameters Check List Table Access Type Register Bit Field Name Non-Mux Address/Data Mux AAD Mux GPMC_CONFIG1_i MUXADDDATA Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 343: Nor Interfacing Timing Parameters Diagram
Asynchronous Synchronous read read Type of access? No read access Synch ronous Asynch ronous read read operation operation SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 344: Gpmc_Config3_I
OEEXTRADELAY GPMC_CONFIG4_i OEONTIME GPMC_CONFIG5_i 27-24 PAGEBURSTACCESSTIME GPMC_CONFIG5_i 20-16 RDACCESSTIME GPMC_CONFIG5_i 12-8 WRCYCLETIME GPMC_CONFIG5_i RDCYCLETIME GPMC_CONFIG6_i 28-24 WRACCESSTIME GPMC_CONFIG6_i 19-16 WRDATAONADMUXBUS 344 Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 345 Access Access Access Access multiplexed access Access Access GPMC_CONFIG6_i 11-8 CYCLE2CYCLEDELAY GPMC_CONFIG6_i CYCLE2CYCLESAMECSEN GPMC_CONFIG6_i CYCLE2CYCLEDIFFCSEN GPMC_CONFIG6_i BUSTURNAROUND GPMC_CONFIG7_i CSVALID SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 346: Nand Formulas Description Table
I = ((OEOnTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay - CSExtraDelay)) * GPMC_FCLK period J = ((AccessTime - OEOffTime) * (TimeParaGranularity + 1) - 0.5 * OEExtraDelay)) * GPMC_FCLK period Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 347: Nand Command Latch Cycle Timing Simplified Example
Delay time - GPMC_CLK rising edge to GPMC_BE0n_CLE/GPMC_BE1n transition Pulse duration - GPMC_ADVn_ALE low Delay time - GPMC_WAIT invalid to first data latching GPMC_CLK edge SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 348 CLKACTIVATIONTIME - 1) is a multiple of 3 F = (2 + 0.5 * CSEXTRADELAY) * GPMC_FCLK period, when (CSRDOFFTIME - Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 349 G = 0.5 * ADVEXTRADELAY * GPMC_FCLK period • Case where GPMCFCLKDIVIDER = 0x1 G = 0.5 * ADVEXTRADELAY * GPMC_FCLK period, when (CLKACTIVATIONTIME and SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 350 I = 0.5 * WEEXTRADELAY * GPMC_FCLK period, when (WEONTIME - CLKACTIVATIONTIME) is a multiple of 3 I = (1 + 0.5 * WEEXTRADELAY) * GPMC_FCLK period, when (WEONTIME - CLKACTIVATIONTIME - Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 351 I = (2 + 0.5 * WEEXTRADELAY) * GPMC_FCLK period, when (WEONTIME - CLKACTIVATIONTIME - 2) is a multiple of 3 SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 352: Synchronous Nor Single Read Simplified Example
NOR single read simplified example where formulas are associated with signal waves. Figure 7-45. Synchronous NOR Single Read Simplified Example GPMC_FCLK GPMC_CLK Valid address nBE1/nBE0 nADV Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 353: Asynchronous Nor Formulas Description Table
F = ((WEOFFTIME - CSONTIME) * (TIMEPARAGRANULARITY + 1) + 0.5 * (WEEXTRADELAY - CSEXTRADELAY)) * GPMC_FCLK period G = CYCLE2CYCLEDELAY * GPMC_FCLK period SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 354: Asynchronous Nor Single Write Simplified Example
Write multiple access is not supported in asynchronous mode. If WRITEMULTIPLE is enabled with WRITETYPE as asynchronous, the GPMC processes single asynchronous accesses. Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 355: Use Case
Write enable (write access only) GPMC_WAIT[1:0] Ready signal from memory device. Indicates when valid burst data is ready to be read SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 356: Gpmc Connection To An External Nor Flash Memory
The following sections demonstrate how to calculate GPMC parameters for three access types: • Synchronous burst read • Asynchronous read • Asynchronous single write Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 357: Useful Timing Parameters On The Memory Side
Read cycle time (GPMC side): Read Access time + access completion • Write cycle time for burst access: Not supported for NOR flash memory SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 358: Synchronous Burst Read Access (Timing Parameters In Clock Cycles)
(access time on memory side) AdvRdOffTime = 2 nADV CsReadOffTime = RdCycleTime OeOffTime = RdCycleTime OeOnTime = 3 A/D bus Valid Address Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 359: Ac Characteristics For Asynchronous Read Access
To complete the access, OEn/CSn signals are driven to high-impedance. AccessTime + 1 + tOEZ is the read cycle time. • Addresses can now be relatched and a new read cycle begun. SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 360: Asynchronous Single Read Access (Timing Parameters In Clock Cycles)
OeOffTime = 10 OeOnTime = 3 Memory-side access time Data Hold time A/D bus Valid Address DATA Valid Address Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 361: Ac Characteristics For Asynchronous Single Write (Memory Side)
For asynchronous single write access, write cycle time is WrCycleTime = WeOffTime + AccessCompletion = WeOffTime + 1. For the AccesCompletion, the GPMC requires 1 cycle of data hold time (CSn de- assertion). SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 362: Asynchronous Single Write Access (Timing Parameters In Clock Cycles)
WeOnTime = 2 (at least 1) At least > 20 ns (tWPH) At least > 25 ns (tWP) ADDRESS ADDRESS A/D bus DATA DATA Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 363: Nand Interface Bus Operations Summary
ADVn WAIT DQ[15:0] Read (asynchronous) Asserted Output Read (synchronous) Running Driven Output Read (burst suspend) Halted Active Output Write Asserted Input SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 364 Table 7-53. NOR Interface Bus Operations Summary (continued) Bus Operation ADVn WAIT DQ[15:0] Output disable Asserted High-Z Standby High-Z High-Z Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 365 Data path to external memory or device: 8- and 16-bit wide • Burst and page access: burst of 4-8-16 Word16 • Supports bus keeping • Supports bus turn around SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 366: Gpmc Registers
Section 7.1.5.33 i = 0 to 6 for GPMC j = 1 to 9 for GPMC k = j - 1 366 Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 367: Gpmc_Revision
During reads, it always returns 0) Normal mode The module is reset AUTOIDLE Internal OCP clock gating strategy Interface clock is free-running Reserved SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 368: Gpmc_Sysstatus
Table 7-57. GPMC_SYSSTATUS Field Descriptions Field Value Description 31-1 Reserved Reserved RESETDONE Internal reset monitoring Internal module reset in on-going Reset completed Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 369: Gpmc_Irqstatus Field Descriptions
FIFOTHRESHOLDSTATUS bytes are available in prefetch mode and at least FIFOTHRESHOLD bytes free places are available in write-posting mode. FIFOEVENTSTATUS bit is reset SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 370: Gpmc_Irqenable
TerminalCountEvent interrupt is masked TerminalCountEvent interrupt is not masked FIFOEVENTENABLE Enables the FIFOEvent interrupt FIFOEvent interrupt is masked FIFOEvent interrupt is not masked Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 371: Gpmc_Timeout_Control Field Descriptions
0-7FFF FFFFh Address of illegal access: A30 (0 for memory region, 1 for GPMC register region) and A29- A0 (1GByte maximum) SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 372: Gpmc_Err_Type
Error validity status - Must be explicitly cleared with a write 1 transaction All error fields no longer valid Error detected and logged in the other error fields Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 373: Gpmc_Config Field Descriptions
A26-A11 are not modified during an external memory access. NANDFORCEPOSTEDWRITE Enables the Force Posted Write feature to NAND Cmd/Add/Data location Disables Force Posted Write Enables Force Posted Write SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 374: Gpmc_Status
WAIT0 de-asserted Reserved Reserved EMPTYWRITEBUFFERSTATUS Stores the empty status of the write buffer Write Buffer is not empty Write Buffer is empty Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 375: Gpmc_Config
24-23 ATTACHEDDEVICEPAGELENGTH Specifies the attached device page (burst) length (1 Word = Interface size) 4 Words 8 Words 16 Words Reserved SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 376 Divides the GPMC.FCLK clock GPMC_CLK frequency = GPMC_FCLK frequency GPMC_CLK frequency = GPMC_FCLK frequency/2 GPMC_CLK frequency = GPMC_FCLK frequency/3 GPMC_CLK frequency = GPMC_FCLK frequency/4 Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 377: Gpmc_Config2_I
Reserved Reserved CSONTIME CS# assertion time from start cycle time 0 GPMC_FCLK cycle 1 GPMC_FCLK cycle ⋮ ⋮ 15 GPMC_FCLK cycles SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 378: Gpmc_Config3_I Field Descriptions
ADV# Add Extra Half GPMC.FCLK cycle ADV Timing control signal is not delayed ADV Timing control signal is delayed of half GPMC_FCLK clock cycle Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 379 7 GPMC_FCLK cycles ADVONTIME ADV# assertion time from start cycle time 0 GPMC_FCLK cycle 1 GPMC_FCLK cycle ⋮ ⋮ 15 GPMC_FCLK cycles SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 380: Gpmc_Config4_I Field Descriptions
OE# Add Extra Half GPMC.FCLK cycle OE Timing control signal is not delayed OE Timing control signal is delayed of half GPMC_FCLK clock cycle Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 381 7 GPMC_FCLK cycles OEONTIME OE# assertion time from start cycle time 0 GPMC_FCLK cycle 1 GPMC_FCLK cycle ⋮ ⋮ 15 GPMC_FCLK cycles SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 382: Gpmc_Config5_I
31 GPMC_FCLK cycles Reserved Reserved RDCYCLETIME Total read cycle time 0 GPMC_FCLK cycle 1 GPMC_FCLK cycle ⋮ ⋮ 31 GPMC_FCLK cycles Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 383: Gpmc_Config6_I
(read to write) or to a different chip-select (read to read and read to write) 0 GPMC_FCLK cycle 1 GPMC_FCLK cycle ⋮ ⋮ 15 GPMC_FCLK cycles SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 384: Gpmc_Config7_I
CSi base address where i = 0 to 3 (16 Mbytes minimum granularity). Bits [5-0] corresponds to A29, A28, A27, A26, A25, and A24. Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 385: Gpmc_Nand_Command_I
Reading data from the GPMC_NAND_DATA_i location or from any location in the associated chip-select memory region activates an asynchronous read access. SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 386: Gpmc_Prefetch_Config1 Field Descriptions
The two next accesses are granted to the PFPW engine ⋮ ⋮ The 16 next accesses are granted to the PFPW engine Reserved Reserved Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 387 DMA request synchronization is enabled. A DMA request protocol is used. Reserved Reserved ACCESSMODE Selects pre-fetch read or write posting accesses Prefetch read mode Write-posting mode SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 388: Gpmc_Prefetch_Config2
Engine is running Resets the FIFO pointer to 0 in prefetch mode and 40h in postwrite mode and starts the engine Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 389: Gpmc_Prefetch_Status Field Descriptions
1 byte remaining to be read or to be writte ⋮ ⋮ 2000h 8 Kbytes remaining to be read or to be written SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 390: Gpmc_Ecc_Config Field Descriptions
Chip-select 1 Chip-select 2 Chip-select 3 Chip-select 4 Chip-select 5 6h-7h Reserved ECCENABLE Enables the ECC feature ECC disabled ECC enabled Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 391: Gpmc_Ecc_Control Field Descriptions
ECC result register 5 selected ECC result register 6 selected ECC result register 7 selected ECC result register 8 selected ECC result register 9 selected SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 392: Gpmc_Ecc_Size_Config Field Descriptions
Selects ECC size for ECC 6 result register ECCSIZE0 selected ECCSIZE1 selected ECC5RESULTSIZE Selects ECC size for ECC 5 result register ECCSIZE0 selected ECCSIZE1 selected Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 393: Gpmc_Ecc_Size_Config
Selects ECC size for ECC 2 result register ECCSIZE0 selected ECCSIZE1 selected ECC1RESULTSIZE Selects ECC size for ECC 1 result register ECCSIZE0 selected ECCSIZE1 selected SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 394: Gpmc_Eccj_Result Field Descriptions
Even Row Parity bit 16 Even Row Parity bit 8 Even Column Parity bit 4 Even Column Parity bit 2 Even Column Parity bit 1 Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 395: Gpmc_Bch_Result0_I
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-85. GPMC_BCH_RESULT2_i Field Descriptions Field Value Description 31-0 BCH_RESULT2_i 0-FFFF FFFFh BCH ECC result, bits 64 to 95 SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 396: Gpmc_Bch_Result3_I
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-88. GPMC_BCH_RESULT4_i Field Descriptions Field Value Description 31-0 BCH_RESULT4_i 0-FFFF FFFFh BCH ECC result, bits 128 to 159 Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 397: Gpmc_Bch_Result5_I
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-90. GPMC_BCH_RESULT6_i Field Descriptions Field Value Description 31-0 BCH_RESULT6_i 0-FFFF FFFFh BCH ECC result, bits 192 to 207 SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 398 Full OCP IP 2.0 Burst support. No wait state. 7.2.1.2 Unsupported OCMC-RAM Features For this device, the OCMC-RAM implementation does not support parity. Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 399: Ocmc Ram Integration
Interface / Functional clock From PRCM 7.2.2.3 OCMC RAM Pin List The OCMC RAM module does not include any external interface pins. SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 400 Prioritized refresh scheduling • Programmable SDRAM refresh rate and backlog counter • Programmable SDRAM timing parameters • Big and little endian modes Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 401: Unsupported Emif Features
Not supported by DID Hardware leveling Silicon bug. Must use software leveling procedure. See AM335x ARM Cortex-A8 Microprocessors (MPUs) Silicon Errata (literature number SPRZ360). SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 402: Emif Connectivity Attributes
DDR_CKE Clock enable DDR_CSn0 Chip select DDR_RASn Row address strobe DDR_CASn Column address strobe DDR_WEn Write enable DDR_BA[2:0] Bank address 402 Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 403 Complimentary data strobes DDR_DQM[1:0] Data masks DDR_D[15:0] Data DDR_ODT On-die termination DDR_RESETn DDR device reset DDR_VREF I/O Voltage reference DDR_VTP VTP compensation pin SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 404: Ddr2/3/Mddr Memory Controller Signals
Clock enable. Used to select Power-Down and Self-Refresh operations. DDR_CASn Active-low column address strobe. DDR_RASn Active-low row address strobe. DDR_WEn Active-low write enable. 404 Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 405: Timing Parameters
OCP interface on the core side for programmability. The subsystem can be used to connect to 16-bit memory devices. Figure 7-89 shows the DDR2/3/mDDR subsystem block diagram. SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 406: Ddr2/3/Mddr Subsystem Block Diagram
DDR2 memory controller parallel to each other. The same peripheral bus is used to write and read data from external memory as well as internal memory-mapped registers. Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 407: Ddr2/3/Mddr Memory Controller Fifo Block Diagram
(one for 8 bits of data). The data macros consists of PHY Data Macro, DLLs and IOs integrated into a macro. SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 408: Digital Filter Configuration
Update on 4 consecutive update requests Update on 5 consecutive update requests Update on 6 consecutive update requests Update on 7 consecutive update requests 408 Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 409: Ibank, Rsize And Pagesize Fields Information
10 row bits 11 row bits RSIZE 12 row bits 13 row bits 14 row bits 15 row bits 16 row bits SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 410: Ocp Address To Ddr2/3/Mddr Address Mapping For Reg_Ibank_Pos=0 And Reg_Ebank_Pos=0
PAGESIZE=1 => 9 bits IBANK=2 => 2 bits PAGESIZE=2 => 10 bits IBANK=3 => 3 bits PAGESIZE=3 => 11 bits 410 Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 411: Ocp Address To Ddr2/3/Mddr Address Mapping For Reg_Ibank_Pos=1 And Reg_Ebank_Pos=0
Thus, the DDR2/3/mDDR controller can keep a maximum of 16 banks (8 internal banks across 2 chip selects) open at a time, but can only interleave among two of them. SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 412: Ocp Address To Ddr2/3/Mddr Address Mapping For Reg_Ibank_Pos=3 And Reg_Ebank_Pos=0
EBANK=1 => 1 bit IBANK=1 => 0 bits RSIZE=1 => 10 bits IBANK=1 => 1 bit PAGESIZE=1 => 9 bits 412 Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 413: Ocp Address To Ddr2/3/Mddr Address Mapping For Reg_Ibank_Pos=3 And Reg_Ebank_Pos=1
PAGESIZE=2 => 10 bits IBANK=3 => 3 bits RSIZE=3 => 12 bits PAGESIZE=3 => 11 bits RSIZE=4 => 13 bits RSIZE=5 => 14 bits SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 414 1. (Highest priority) SDRAM refresh request due to Refresh Must level of refresh urgency reached (see Section 7.3.3.5.5). Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 415 The commands in the Command FIFO can be mapped to 2 classes of service namely 1 and 2. The mapping of commands to a particular class of service can be done based on the priority or the connection SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 416: Refresh Modes
Backlog count is greater than 7. Indicates that the refresh backlog of REFR commands is getting excessive Refresh Must and DDR2/3/mDDR memory controller should perform an auto refresh cycle before servicing any new memory access requests. Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 417: Filter Configurations For Performance Counters
1. Write leveling 2. Read DQS gate training 3. Read data eye training Read and write leveling is only supported to DDR3 memory. SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 418 7.3.3.10 Emulation Considerations The DDR2/3/mDDR memory controller will remain fully functional during emulation halts to allow emulation access to external memory. Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 419 DDR2 termination resistor value from SDRAM Config register DDR_A[5:3] Additive latency = 0 DDR_A[2] reg_ddr_term[0] DDR2 termination resistor value from SDRAM Config register SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 420 In power-down mode, the memory controller does not stop the clocks DDR_CLK to the SDRAM. The memory controller maintains DDR_CKE low to maintain the power-down state. Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 421 8. SDRAM Timing 2 Shadow register (SDRTIM2SR) 9. SDRAM Timing 3 register (SDRTIM3) 10. SDRAM Timing 3 Shadow register (SDRTIM3SR) 11. Power Management Control register (PMCR) SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 422: 7.3.5 Emif4D Registers
Section 7.3.5.4 SDRAM_REF_CTRL Section 7.3.5.5 SDRAM_REF_CTRL_SHDW Section 7.3.5.6 SDRAM_TIM_1 Section 7.3.5.7 SDRAM_TIM_1_SHDW Section 7.3.5.8 SDRAM_TIM_2 Section 7.3.5.9 SDRAM_TIM_2_SHDW Section 7.3.5.10 422 Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 423 CONNID_COS_2_MAP Connection ID to Class of Service 2 Mapping Register Section 7.3.5.37 120h RD_WR_EXEC_THRSH Read Write Execution Threshold Register Section 7.3.5.38 SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 424: Emif_Mod_Id_Rev Register
Used to distinguish between old and current schemes. 29-28 Reserved 27-16 reg_module_id EMIF module ID. 15-11 reg_rtl_version RTL Version. 10-8 reg_major_revision Major Revision. Reserved reg_minor_revision Minor Revision. Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 425: Status Register
Reflects the value on the phy_ready port (active high) that defines whether the DDR PHY is ready for normal operation. Reserved SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 426: Sdram_Config Register
Value of 0, 1, 2, and 3 (CAS write latency of 5, 6, 7, and 8) are supported. Use the lowest value supported for best performance. All other values are reserved. Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 427 512-word page (9 column bits), set to 2 for 1024-word page (10 column bits), and set to 3 for 2048-word page (11 column bits). All other values are reserved. SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 428: Sdram_Config_2 Register
OCP Address to DDR2/3/mDDR Address Mapping. 26-6 Reserved Reserved Reserved. Reserved Reserved Reserved. Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 429: Sdram_Ref_Ctrl Register
If reg_refresh_rate < (8*reg_t_rfc)+reg_t_rp+reg_t_rcd+20 then it will be loaded with (8*reg_t_rfc)+reg_t_rp+reg_t_rcd+20. This is done to avoid lock-up situations when illegal values are programmed. SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 430: Sdram_Ref_Ctrl_Shdw Register
This field is loaded into reg_refresh_rate field in SDRAM Refresh Control register when SIdleAck is asserted. This register is not auto corrected when the value is invalid. Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 431: Sdram_Tim_1 Register
For an 8-bank DDR2 and DDR3, this field must be equal to ((tFAW/(4*tCK))-1). reg_t_wtr Minimum number of DDR clock cycles from last Write to Read, minus one. SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 432: Sdram_Tim_1_Shdw Register
Shadow field for reg_t_wtr. This field is loaded into reg_t_wtr field in SDRAM Timing 1 register when SIdleAck is asserted. Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 433: Sdram_Tim_2 Register
Pre-charge command for DDR2 and DDR3, minus one. reg_t_cke Minimum number of DDR clock cycles between pad_cke_o changes, minus one. SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 434: Sdram_Tim_2_Shdw Register
Shadow field for reg_t_cke. This field is loaded into reg_t_cke field in SDRAM Timing 2 register when SIdleAck is asserted. Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 435: Sdram_Tim_3 Register
This field is only applicable for mDDR. This field must be programmed to 0xF for other SDRAM types. SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 436: Sdram_Tim_3_Shdw Register
Shadow field for reg_t_ras_max. This field is loaded into reg_t_ras_max field in SDRAM Timing 3 register when SIdleAck is asserted. Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 437: Pwr_Mgmt_Ctrl Register
Set to 1 for Clock Stop, set to 2 for Self Refresh, and set to 4 for Power-Down. All other values will disable automatic power management. SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 438 Note: After updating this field, at least one dummy read access to SDRAM is required for the new value to take affect. Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 439: Pwr_Mgmt_Ctrl_Shdw Register
Shadow field for reg_cs_tim. This field is loaded into reg_cs_tim field in Power Management Control register when SIdleAck is asserted. SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 440: Interface Configuration Register
OCP Command FIFO. A value of N will be equal to N x 16 clocks. Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 441: Interface Configuration Value 1 Register
Reserved for future use. 15-8 REG_WR_FIFO_DEPTH 0x14 Write Data FIFO depth for a particular configuration. REG_CMD_FIFO_DEPTH R Command FIFO depth for a particular configuration. SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 442: Interface Configuration Value 2 Register
0x16 SDRAM Read Data FIFO depth for a particular configuration. REG_RCMD_FIFO_DEPT R 0x16 Read Command FIFO depth for a particular configuration. Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 443: Perf_Cnt_1 Register
32-bit counter that can be configured as specified in the Performance Counter Config Register and Performance Counter Master Region Select Register. SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 444: Perf_Cnt_2 Register
32-bit counter that can be configured as specified in the Performance Counter Config Register and Performance Counter Master Region Select Register. Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 445: Perf_Cnt_Cfg Register
Chip Select filter enable for Performance Counter 1 register. 13-4 Reserved reg_cntr1_cfg Filter configuration for Performance Counter 1. For details, see the table titled "Filter Configurations for Performance Counters". SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 446: Perf_Cnt_Sel Register
MAddrSpace for Performance Counter 2 register. 15-8 reg_mconnid1 MConnID for Performance Counter 1 register. Reserved reg_region_sel1 MAddrSpace for Performance Counter 1 register. Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 447: Perf_Cnt_Tim Register
Reset Description 31-0 reg_total_time 32-bit counter that continuously counts number for m_clk cycles elapsed after EMIF is brought out of reset. SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 448: Read_Idle_Ctrl Register
The Read Idle Interval field determines the maximum interval ((reg_read_idle_interval-1)*64 clock cycles) between read idle detections or force. A value of zero disables the read idle function. Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 449: Read_Idle_Ctrl_Shdw Register
Shadow field for reg_read_idle_interval. This field is loaded into reg_read_idle_interval field in Read Idle Control register when SIdleAck is asserted. SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 450: Irqstatus_Raw_Sys Register
Raw status of system OCP interrupt. Write 1 to set the (raw) status, mostly for debug. Writing a 0 has no effect. Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 451: Irqstatus_Sys Register
Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, i.e. even if not enabled). Writing a 0 has no effect. SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 452: Irqenable_Set_Sys Register
Writing a 1 will enable the interrupt, and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect. Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 453: Irqenable_Clr_Sys Register
Writing a 1 will disable the interrupt, and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect. SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 454: Zq_Config Register
This field supports between one refresh period to 256 ms between ZQCS calibration commands. Refresh period is defined by reg_refresh_rate in SDRAM Refresh Control register. Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 455: Read-Write Leveling Ramp Window Register
P_WIN The value programmed is minus one the required value. Refresh period is defined by reg_refresh_rate in SDRAM Refresh Control register. SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 456: Read-Write Leveling Ramp Control Register
Incremental write leveling interval during ramp window. Number of reg_rdwrlvlinc_rmp_pre intervals between incremental write leveling. A value of 0 will disable incremental write leveling during ramp window. Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 457: Read-Write Leveling Control Register
Incremental write leveling interval. Number of reg_rdwrlvlinc_pre intervals between incremental write leveling. A value of 0 will disable incremental write leveling. SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 458: Ddr_Phy_Ctrl_1 Register
11 = Half thevenin load. Effective ODT is equivalent to 2x the output driver impedance setting in DDR_DATAx_IOCTRL.io_config_i register bits. Reserved Reserved. Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 459: Ddr_Phy_Ctrl_1 Register Field Descriptions
The maximum read latency supported by the DDR PHY is equal to CAS latency plus 7 clock cycles. The minimum read latency must be equal to CAS latency plus 2 clock cycle. SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 460: Ddr_Phy_Ctrl_1_Shdw Register
00 = ODT off. 01 = ODT off. 10 = Full thevenin load. 11 = Half thevenin load. Reserved Reserved. Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 461 The maximum read latency supported by the DDR PHY is equal to CAS latency plus 7 clock cycles. The minimum read latency must be equal to CAS latency plus 2 clock cycle. SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 462: Priority To Class Of Service Mapping Register
Class of service for commands with priority of 0. Value can be 1 or 2. Setting a value of 0 or 3 will not assign any class of service. Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 463: Connection Id To Class Of Service 1 Mapping Register
1 = mask connection ID bit 0. 2 = mask connection ID bits 1:0. 3 = mask connection ID bits 2:0. SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 464: Connection Id To Class Of Service 2 Mapping Register
2 = mask connection ID bits 1:0. 3 = mask connection ID bits 2:0. REG_CONNID_3_COS_2 R/W Connection ID value 3 for class of service 2. Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 465 1 = mask connection ID bit 0. 2 = mask connection ID bits 1:0. 3 = mask connection ID bits 2:0. SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 466: Read Write Execution Threshold Register
Number of SDRAM read bursts after which the EMIF arbitration will switch to executing write commands. The value programmed is always minus one the required number. Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 467: Memory-Mapped Registers For Ddr2/3/Mddr Phy
0 DQS Gate Training Init Mode Ratio Selection Register DATA0_REG_PHY_FIFO_WE_SLAVE_RATI DDR PHY Data Macro 0x108 0 DQS Gate Slave Ratio Register SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 468 DATA1_REG_PHY_USE_RANK0_DELAYS DDR PHY Data Macro 0x1D8 1 Delay Selection Register DATA1_REG_PHY_DLL_LOCK_DIFF_0 DDR PHY Data Macro 0x1DC 1 DLL Lock Difference Register Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 469: Ddr Phy Command 0/1/2 Address/Command Slave Ratio Register
(incoming clock jitter (pp) + delay line jitter (pp)). SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 470: Ddr Phy Command 0/1/2 Invert Clockout Selection Register( Cmd0/1/2_Reg_Phy_Invert_Clkout_0)
256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 471: Ddr Phy Data Macro 0/1 Write Leveling Init Ratio Register ( Data0/1_Reg_Phy_Wrlvl_Init_Ratio_0)
Reserved Reserved WRLVL_INIT_RATIO The user programmable init ratio used by Write Leveling FSM when _CS0 DATA0/1_REG_PHY_WRLVL_INIT_MODE_0 register value set to 1 SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 472: Ddr Phy Data Macro 0 Write Leveling Init Mode Ratio Selection Register
Reserved Reserved GATELVL_INIT_RATIO_CS0 The user programmable init ratio used by DQS Gate Training FSM when DATA0/1/_REG_PHY_GATELVL_INIT_MODE_0 register value set to 1. Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 473: Ddr Phy Data Macro 0/1 Dqs Gate Training Init Mode Ratio Selection Register
(DATA0/1_REG_PHY_FIFO_WE_SLAVE_RATIO_0) Field Descriptions Field Value Description 31-20 Reserved Reserved 19-10 Reserved Reserved RD_DQS_GATE _SLAVE_RATIO_CS0 Ratio value for fifo we for CS0. SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 474: Ddr Phy Data Macro 0/1 Write Data Slave Ratio Register
DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 475: Ddr Phy Data Macro 0/1 Delay Selection Register (Data0/1_Reg_Phy_Use_Rank0_Delays)
Each Rank uses its own delay. (Recommended). This is applicable only in case of DDR3 Rank 0 delays are used for all ranks. This must be set to 1 for DDR2 and mDDR. SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 476 – For each syndrome polynomial in continuous mode 7.4.1.2 Unsupported ELM Features There are no unsupported ELM features in this device. Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 477: Elm Integration
100 MHz CORE_CLKOUTM4 / 2 pd_per_l4ls_gclk From PRCM 7.4.2.3 ELM Pin List The ELM module does not include any external interface pins. SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 478: Local Power Management Features
ELM_IRQ Error-location interrupt for syndrome polynomial 3 LOC_VALID_3 LOCATION_MASK_3 ELM_IRQSTATUS[2] ELM_IRQENABLE[2] ELM_IRQ Error-location interrupt for syndrome polynomial 2 LOC_VALID_2 LOCATION_MASK_2 478 Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 479 ECC_CORRECTABLE is 0. If the engine completes early, the associated error-location registers ELM_ERROR_LOCATION_0_i to ELM_ERROR_LOCATION_15_i are not updated (i = 0 to 7). SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 480: Elm_Location_Status_I Value Decoding Table
ELM_PAGE_CTRL[i] SECTOR_i bit fields (i = 0 to 7) are processed as usual, but are essentially ignored. The CPU must manually poll the ELM_IRQSTATUS bits to check for their status. Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 481: Elm Processing Initialization
ECC_NB_ERRORS first ECC_ERROR_LOCATION registers. ELM_ERROR_LOCATION_1_i[12:0] It is the software responsibility to correct errors in ECC_ERROR_LOCATION the data buffer. ELM_ERROR_LOCATION_15_i[12:0] ECC_ERROR_LOCATION SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 482: Elm Processing Completion For
ELM_SYSCONFIG[1] SOFTRESET Wait until reset is done. ELM_SYSSTATUS[0] RESETDONE Configure the slave interface power management: ELM_SYSCONFIG[4:3] SIDLEMODE Smart idle is used. 482 Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 483 7 to bit 0, then from bit 15 to bit 8. Based on this convention, an address table of the data buffer can be built. NAND memory addresses in Table 7-172 are given in decimal format. SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 484 0x420 Sets the ELM in page mode (4 blocks in a page) ELM_PAGE_CTRL[0] SECTOR_0 ELM_PAGE_CTRL[1] SECTOR_1 ELM_PAGE_CTRL[2] SECTOR_2 ELM_PAGE_CTRL[3] SECTOR_3 484 Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 485 All errors were successfully located. Read the process exit status for syndrome ELM_LOCATION_STATUS_i[8] ECC_CORRECTABLE polynomial 1: (i=1) All errors were successfully located. SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 486 Read the errors location bit addresses for ELM_ERROR_LOCATION_0_i (i=1) 0x3E8 syndrome polynomial 2 of the first registers: Clear the ELM_IRQSTATUS register. ELM_IRQSTATUS 0x1FF Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 487: 7.4.5 Elm Registers
ELM_LOCATION_STATUS_i Register Section 7.4.5.15 (100h × i) 880h-8BCh + ELM_ERROR_LOCATION_0-15_i ELM_ERROR_LOCATION_0-15_i Section 7.4.5.16 (100h × i) Registers i = 0 to 8 SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 488: Elm Revision Register (Elm_Revision)
Internal OCP clock gating strategy. (No module visible impact other than saving power.) OCP clock is free-running. Automatic internal OCP clock gating strategy is applied based on the OCP interface activity. Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 489: Elm System Status Register (Elm_Sysstatus)
From hardware perspective, the reset state is 0. From software user perspective, when the accessible module is 1. Reset is on-going Reset is done (completed) SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 490: Elm Interrupt Status Register (Elm_Irqstatus)
Error-location status for syndrome polynomial 3. Read: No syndrome processed or process in progress. Read: Error-location process completed. Write: No effect. Write: Clear interrupt. Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 491: Elm Interrupt Status Register (Elm_Irqstatus) Field Descriptions
Error-location status for syndrome polynomial 0. Read: No syndrome processed or process in progress. Read: Error-location process completed. Write: No effect. Write: Clear interrupt. SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 492: Elm Interrupt Enable Register (Elm_Irqenable)
Error-location interrupt mask bit for syndrome polynomial 1. Disable interrupt. Enable interrupt. LOCATION_MASK_0 Error-location interrupt mask bit for syndrome polynomial 0. Disable interrupt. Enable interrupt. Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 493: Elm Location Configuration Register (Elm_Location_Config)
Maximum size of the buffers for which the error-location engine is used, in number of nibbles (4-bits entities) 15-2 Reserved Reserved ECC_BCH_LEVEL Error correction level. 4 bits. 8 bits. 16 bits. Reserved. SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 494: Elm Page Definition Register (Elm_Page_Ctrl)
Set to 1 if syndrome polynomial 0 is part of the page in page mode. Must be 0 in continuous mode. Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 495: Elm_Syndrome_Fragment_0_I Register
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-184. ELM_SYNDROME_FRAGMENT_2_i Register Field Descriptions Field Value Description 31-0 SYNDROME_2 0-FFFF FFFFh Syndrome bits 64 to 95. SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 496: Elm_Syndrome_Fragment_3_I Register
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-187. ELM_SYNDROME_FRAGMENT_5_i Register Field Descriptions Field Value Description 31-0 SYNDROME_5 0-FFFF FFFFh Syndrome bits 160 to 191. Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 497: Elm_Syndrome_Fragment_6_I Register
All errors were successfully located. Number of errors and error locations are valid. Reserved Reserved ECC_NB_ERROR 0-1Fh Number of errors detected and located. SPRUH73H – October 2011 – Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 498: Elm_Error_Location_0-15_I Registers
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-190. ELM_ERROR_LOCATION_0-15_i Registers Field Descriptions Field Value Description 31-13 Reserved Reserved 12-0 ECC_ERROR_LOCATION 0-1FFFh Error-location bit address. Memory Subsystem SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 499 This chapter describes the PRCM of the device..........................Topic Page ............... Power, Reset, and Clock Management SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 500: Functional And Interface Clocks
A typical module has one interface clock, but modules with multiple interface clocks may also exist (that is, when connected to multiple interconnect buses). Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 501: Master Module Standby-Mode Settings
However, it is not efficient from a power-saving perspective because it never allows the output clocks of the PRCM module to be gated SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 502: Master Module Standby Status
502 Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 503: Idle States For A Slave Module
PRCM module can gate all clocks to the module (that is, the module is completely disabled).. Reserved SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 504: Module Clock Enabling Condition
This allows the PRCM module to individually activate and gate each clock domain of the device Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 505: Generic Clock Domain
All domain clocks gated IDLE_TRANSITION ACTIVE INACTIVE Domain sleep conditions not satisfied A wake-up request is received prcm-003 SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 506: Clock Domain States
(see Figure). A power domain can be turned on and off without affecting the other parts of the device. Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 507: Generic Power Domain Architecture
State Description Logic is fully powered Logic power switches are off. All the logic (DFF) is lost SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 508: Power Domain Control And Status Registers
The device voltage is automatically adapted to maintain performance of the device Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 509: Typical Power Modes
Power domains: PD_PER = ON PD_MPU = OFF PD_GFX = OFF PD_WKUP = ON DDR is in self-refresh. SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 510 PLL to remain locked) and the module must be configured appropriately for wakeup by configuring it to generate an interrupt to the MPUSS. Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 511 RTCSS: pmic_power_en and ext_wakeup. Figure 8-5 gives a high level view of system which implements the RTC-only mode. SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 512: High Level System View For Rtc-Only Mode
EXT_WAKEUP0 is connected to a wakeup source See the device datasheet for more information on these signals. Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 513: Usb Wakeup Use Cases Supported In System Sleep States
DSCOUNT configured in DEEPSLEEP_CTRL register. SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 514 Power management system between Cortex A8 MPU and Cortex M3. Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 515: System Level View Of Power Management Of Cortex A8 Mpu And Cortex M3
The Cortex-M3 handles all of the low-level power management control of the AM335x. A firmware binary is provided by Texas Instruments that includes all of the necessary functions to achieve low power modes. Inter-Processor Communication (IPC) registers (ipc_msg_regx, located in the...
Page 516: Ipc Mechanism
2. Turns off the MPU power domains. 3. Configures the system for disabling MOSC when CM3 executes WFI. 516 Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 517 The PRCM is structured using the architectural concepts presented in the 5000x Power Management Framework. This framework provides: SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 518 This interface provides PRM management of several device-level features which are not specific to any single power domain. This PRM interface controls signals to/from the device for global control: Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 519 The ADPLLS module is used for the Core, Display, ARM Subsystem and DDR PLLs The ADPLLLJ module is used for the peripheral functional clocks SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 520 CLKOUTX2: Secondary 2x Output • CLKOUT: Primary output clock • CLKDCOLDO: Oscillator (DCO) output clock with no bypass Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 521: Output Clocks In Locked Condition
PLL to be locked. For more details, see the configuration procedure for each PLL. SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 522: Basic Structure Of The Adplllj
Oscillator (DCO) output clock before post-division in VDDLDOOUT domain. Bypass option is not available on this output. CLKDCOLDO = (M / (N+1))*CLKINP. Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 523: Output Clocks In Locked Condition
SSC is disabled only after completion of one full cycle of the triangular pattern given by the modulation frequency. This is done in order to maintain the average frequency. SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 524 Core PLL comprises an ADPLLS with HSDIVIDER and additional dividers and muxes located in the PRCM as shown in Figure 8-10. Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 525: Core Pll
ALT_CLKs are to be used for internal test purpose and should not be used in functional mode. SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 526: Pll And Clock Frequences
CLKINBYPASS input is driven on the M4, M5, and M6 outputs. CLKINBYPASS defaults to the master oscillator input (typically 24 MHz). 526 Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 527: Bus Interface Clocks
The Per PLL provides the source for peripheral functional clocks. The Per PLL comprises an ADPLLLJ and additional dividers and muxes located in the PRCM as shown SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 528: Peripheral Pll Structure
Not all interfaces and peripheral modules are available in OPP50. For more information, see AM335x ARM Cortex-A8 Microprocessors (MPUs) Silicon Errata (literature number SPRZ360). 528 Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 529 The Cortex A8 MPU subsystem includes an internal ADPLLS for generating the required Cortex A8 MPU clocks. This PLL is driven by the master oscillator output with control provided by PRCM registers. SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 530: Mpu Subsystem Pll Structure
CM_DIV_M2_DPLL_MPU.DPLL_CLKOUT_DIVCHACK for a toggle (a change from 0 to 1 or 1 to 0) to see if the change was acknowledged by the PLL. Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 531: Display Pll Structure
6. Wait for CM_IDLEST_DPLL_DISP.ST_DPLL_CLK = 1 to ensure PLL is locked (CM_IDLEST_DPLL_DISP.ST_MN_BYPASS should also change to 0 to denote the PLL is out of bypass mode). SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 532: Ddr Pll Structure
6. Wait for CM_IDLEST_DPLL_DDR.ST_DPLL_CLK = 1 to ensure PLL is locked (CM_IDLEST_DPLL_DDR.ST_MN_BYPASS should also change to 0 to denote the PLL is out of bypass mode). Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 533: Clkout Signals
(Default: 0) To DMTIMER0 All mux selections are in PRCM unless explicitly shown otherwise in the diagrams. SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 534: Timer Clock Selection
The 32K Osc requires an external 32768-Hz crystal. All mux selections are in PRCM unless explicitly shown otherwise in the diagrams. Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 535: Rtc, Vtp, And Debounce Clock Selection
Local reset: it affects part of the device (1 power domain for example) • S/W reset: it is initiated by software • H/W reset: it is hardware driven SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 536: Reset Sources
IO cell controls from IPs for all the IOs with a few exceptions (see datasheet for details) are driven by Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 537 The warm reset assumes that clocks and power to the chip are stable from assertion through deassertion, whereas during the cold reset, the power supplies can become stable during assertion SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 538: External System Reset
• Emulation reset (Cold or warm from ICEPICK) • Reset requestor • SW cold/warm reset Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 539: Warm Reset Sequence (External Warm Reset Source)
SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 540: Warm Reset Sequence (Internal Warm Reset Source)
Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 541 Power, Reset, and Clock Management www.ti.com 8.1.7.5 Reset Characteristics The following table shows characteristic of each reset source. SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 542 Some special IOs/Muxing registers like test, emulation, GEMAC Switch (When under reset isolation mode), etc related will not be affected under warm reset conditions. 542 Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 543 If the RTC-only mode is not required, then PORz and RTC_PORz needs to be shorted. For power-up sequencing with respect to RTC_PORz, see the device specific datasheet. SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 544 The following table shows how the device core logic is partitioned into two core logic voltage domains and four power domains. The table lists which voltage and power domain a functional module belongs. 544 Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 545: Core Logic Voltage And Power Domains
GPIO0 DMTIMER0_dmc DMTIMER1 UART0 I2C0 WDT1 PD_WKUP SmartReflex_c2_0 This is non-switchable and cannot be shut SmartReflex_c2_1 L4_WKUP SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 546 VDD_RTC PD_RTC VDD for 32 768 Hz Crystal Osc VDD for IO for the alarm pin 546 Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 547 8. PRCM will initiate and wait for completion of PM protocol to enable the modules (IdleReq/IdleAck). SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 548: Cm_Per Registers
Section 8.1.12.1.37 CM_PER_EMIF_FW_CLKCTRL Section 8.1.12.1.38 CM_PER_EPWMSS0_CLKCTRL Section 8.1.12.1.39 CM_PER_EPWMSS2_CLKCTRL Section 8.1.12.1.40 CM_PER_L3_INSTR_CLKCTRL Section 8.1.12.1.41 CM_PER_L3_CLKCTRL Section 8.1.12.1.42 548 Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 549 Section 8.1.12.1.57 144h CM_PER_CPSW_CLKSTCTRL Section 8.1.12.1.58 148h CM_PER_LCDC_CLKSTCTRL Section 8.1.12.1.59 14Ch CM_PER_CLKDIV32K_CLKCTRL Section 8.1.12.1.60 150h CM_PER_CLK_24MHZ_CLKSTCT Section 8.1.12.1.61 SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 550: Cm_Per_L4Ls_Clkstctrl Register
0x0 = Inact : Corresponding clock is gated 0x1 = Act : Corresponding clock is active Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 551 0x2 = SW_WKUP : SW_WKUP: Start a software forced wake-up transition on the domain. 0x3 = Reserved : Reserved. SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 552: Cm_Per_L3S_Clkstctrl Register
0x2 = SW_WKUP : SW_WKUP: Start a software forced wake-up transition on the domain. 0x3 = Reserved : Reserved. Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 553: Cm_Per_L4Fw_Clkstctrl Register
0x2 = SW_WKUP : SW_WKUP: Start a software forced wake-up transition on the domain. 0x3 = Reserved SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 554: Cm_Per_L3_Clkstctrl Register
0x2 = SW_WKUP : SW_WKUP: Start a software forced wake-up transition on the domain. 0x3 = Reserved : Reserved. Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 555: Cm_Per_Cpgmac0_Clkctrl Register
Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen. 0x3 = RESERVED : Reserved SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 556: Cm_Per_Lcdc_Clkctrl Register
Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen. 0x3 = RESERVED : Reserved Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 557: Cm_Per_Usb0_Clkctrl Register
Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen. 0x3 = RESERVED : Reserved SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 558: Cm_Per_Tptc0_Clkctrl Register
Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen. 0x3 = RESERVED : Reserved Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 559: Cm_Per_Emif_Clkctrl Register
Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen. 0x3 = RESERVED : Reserved SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 560: Cm_Per_Ocmcram_Clkctrl Register
Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen. 0x3 = RESERVED : Reserved Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 561: Cm_Per_Gpmc_Clkctrl Register
Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen. 0x3 = RESERVED : Reserved SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 562: Cm_Per_Mcasp0_Clkctrl Register
Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen. 0x3 = RESERVED : Reserved Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 563: Cm_Per_Uart5_Clkctrl Register
Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen. 0x3 = RESERVED : Reserved SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 564: Cm_Per_Mmc0_Clkctrl Register
Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen. 0x3 = RESERVED : Reserved Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 565: Cm_Per_Elm_Clkctrl Register
Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen. 0x3 = RESERVED : Reserved SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 566: Cm_Per_I2C2_Clkctrl Register
Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen. 0x3 = RESERVED : Reserved Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 567: Cm_Per_I2C1_Clkctrl Register
Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen. 0x3 = RESERVED : Reserved SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 568: Cm_Per_Spi0_Clkctrl Register
Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen. 0x3 = RESERVED : Reserved Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 569: Cm_Per_Spi1_Clkctrl Register
Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen. 0x3 = RESERVED : Reserved SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 570: Cm_Per_L4Ls_Clkctrl Register
Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen. 0x3 = RESERVED : Reserved Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 571: Cm_Per_L4Fw_Clkctrl Register
Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen. 0x3 = RESERVED : Reserved SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 572: Cm_Per_Mcasp1_Clkctrl Register
Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen. 0x3 = RESERVED : Reserved Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 573: Cm_Per_Uart1_Clkctrl Register
Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen. 0x3 = RESERVED : Reserved SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 574: Cm_Per_Uart2_Clkctrl Register
Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen. 0x3 = RESERVED : Reserved Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 575: Cm_Per_Uart3_Clkctrl Register
Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen. 0x3 = RESERVED : Reserved SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 576: Cm_Per_Uart4_Clkctrl Register
Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen. 0x3 = RESERVED : Reserved Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 577: Cm_Per_Timer7_Clkctrl Register
Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen. 0x3 = RESERVED : Reserved SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 578: Cm_Per_Timer2_Clkctrl Register
Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen. 0x3 = RESERVED : Reserved Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 579: Cm_Per_Timer3_Clkctrl Register
Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen. 0x3 = RESERVED : Reserved SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 580: Cm_Per_Timer4_Clkctrl Register
Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen. 0x3 = RESERVED : Reserved Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 581: Cm_Per_Gpio1_Clkctrl Register
Functional clocks are guaranteed to stay present. As long as in this configuration, power domain sleep transition cannot happen. 0x3 = RESERVED : Reserved SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 582: Cm_Per_Gpio2_Clkctrl Register
Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen. 0x3 = RESERVED : Reserved Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 583: Cm_Per_Gpio3_Clkctrl Register
Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen. 0x3 = RESERVED : Reserved SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 584: Cm_Per_Tpcc_Clkctrl Register
Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen. 0x3 = RESERVED : Reserved Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 585: Cm_Per_Dcan0_Clkctrl Register
Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen. 0x3 = RESERVED : Reserved SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 586: Cm_Per_Dcan1_Clkctrl Register
Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen. 0x3 = RESERVED : Reserved Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 587: Cm_Per_Epwmss1_Clkctrl Register
Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen. 0x3 = RESERVED : Reserved SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 588: Cm_Per_Emif_Fw_Clkctrl Register
Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen. 0x3 = RESERVED : Reserved Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 589: Cm_Per_Epwmss0_Clkctrl Register
Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen. 0x3 = RESERVED : Reserved SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 590: Cm_Per_Epwmss2_Clkctrl Register
Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen. 0x3 = RESERVED : Reserved Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 591: Cm_Per_L3_Instr_Clkctrl Register
Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen. 0x3 = RESERVED : Reserved SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 592: Cm_Per_L3_Clkctrl Register
Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen. 0x3 = RESERVED : Reserved Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 593: Cm_Per_Ieee5000_Clkctrl Register
Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen. 0x3 = RESERVED : Reserved SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 594: Cm_Per_Pru_Icss_Clkctrl Register
Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen. 0x3 = RESERVED : Reserved Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 595: Cm_Per_Timer5_Clkctrl Register
Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen. 0x3 = RESERVED : Reserved SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 596: Cm_Per_Timer6_Clkctrl Register
Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen. 0x3 = RESERVED : Reserved Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 597: Cm_Per_Mmc1_Clkctrl Register
Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen. 0x3 = RESERVED : Reserved SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 598: Cm_Per_Mmc2_Clkctrl Register
Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen. 0x3 = RESERVED : Reserved Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 599: Cm_Per_Tptc1_Clkctrl Register
Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen. 0x3 = RESERVED : Reserved SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 600: Cm_Per_Tptc2_Clkctrl Register
Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen. 0x3 = RESERVED : Reserved Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 601: Cm_Per_Spinlock_Clkctrl Register
Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen. 0x3 = RESERVED : Reserved SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 602: Cm_Per_Mailbox0_Clkctrl Register
Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen. 0x3 = RESERVED : Reserved Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 603: Cm_Per_L4Hs_Clkstctrl Register
0x2 = SW_WKUP : SW_WKUP: Start a software forced wake-up transition on the domain. 0x3 = Reserved : Reserved. SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 604: Cm_Per_L4Hs_Clkctrl Register
Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen. 0x3 = RESERVED : Reserved Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 605: Cm_Per_Ocpwp_L3_Clkstctrl Register
0x2 = SW_WKUP : SW_WKUP: Start a software forced wake-up transition on the domain. 0x3 = Reserved : Reserved. SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 606: Cm_Per_Ocpwp_Clkctrl Register
Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen. 0x3 = RESERVED : Reserved Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 607: Cm_Per_Pru_Icss_Clkstctrl Register
0x2 = SW_WKUP : SW_WKUP: Start a software forced wake-up transition on the domain. 0x3 = Reserved : Reserved. SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 608: Cm_Per_Cpsw_Clkstctrl Register
0x2 = SW_WKUP : SW_WKUP: Start a software forced wake-up transition on the domain. 0x3 = Reserved : Reserved. Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 609: Cm_Per_Lcdc_Clkstctrl Register
0x2 = SW_WKUP : SW_WKUP: Start a software forced wake-up transition on the domain. 0x3 = Reserved : Reserved. SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 610: Cm_Per_Clkdiv32K_Clkctrl Register
Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen. 0x3 = RESERVED : Reserved Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 611: Cm_Per_Clk_24Mhz_Clkstctrl Register
CM_WKUP_CONTROL_CLKCTRL This register manages the Control Module clocks. Section 8.1.12.2.2 CM_WKUP_GPIO0_CLKCTRL This register manages the GPIO0 clocks. Section 8.1.12.2.3 SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 612 This register provides controls over the DPLL. Section 8.1.12.2.22 CM_AUTOIDLE_DPLL_CORE This register provides automatic control over the DPLL Section 8.1.12.2.23 activity. 612 Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 613 This register manages the SmartReflex0 clocks. Section 8.1.12.2.49 KCTRL CM_WKUP_TIMER1_CLKCTRL This register manages the TIMER1 clocks. Section 8.1.12.2.50 SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 614 CM_DIV_M6_DPLL_CORE This register provides controls over the CLKOUT3 o/p of Section 8.1.12.2.54 the HSDIVIDER. [warm reset insensitive] Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 615: Cm_Wkup_Clkstctrl Register
0x0 = Inact : Corresponding clock is gated 0x1 = Act : Corresponding clock is active SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 616 0x2 = SW_WKUP : SW_WKUP: Start a software forced wake-up transition on the domain. 0x3 = Reserved : Reserved. Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 617: Cm_Wkup_Control_Clkctrl Register
Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen. 0x3 = RESERVED : Reserved SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 618: Cm_Wkup_Gpio0_Clkctrl Register
Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen. 0x3 = RESERVED : Reserved Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 619: Cm_Wkup_L4Wkup_Clkctrl Register
0x3 = Disable : Module is disabled and cannot be accessed 15-2 Reserved MODULEMODE Control the way mandatory clocks are managed. SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 620: Cm_Wkup_Timer0_Clkctrl Register
Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen. 0x3 = RESERVED : Reserved Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 621: Cm_Wkup_Debugss_Clkctrl Register
Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen. 0x3 = RESERVED : Reserved SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 622: Cm_L3_Aon_Clkstctrl Register
0x2 = SW_WKUP : SW_WKUP: Start a software forced wake-up transition on the domain. 0x3 = Reserved : Reserved. Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 623: Cm_Autoidle_Dpll_Mpu Register
Table 8-99. CM_AUTOIDLE_DPLL_MPU Register Field Descriptions Field Type Reset Description 31-3 Reserved AUTO_DPLL_MODE This feature is not supported. SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 624: Cm_Idlest_Dpll_Mpu Register
0x0 = DPLL_UNLOCKED : DPLL is either in bypass mode or in stop mode. 0x1 = DPLL_LOCKED : DPLL is LOCKED Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 625: Cm_Ssc_Deltamstep_Dpll_Mpu Register
Reserved 19-18 DELTAMSTEP_INTEGER R/W Integer part for DeltaM coefficient 17-0 DELTAMSTEP_FRACTIO R/W Fractional part for DeltaM coefficient SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 626: Cm_Ssc_Modfreqdiv_Dpll_Mpu Register
Set the Exponent component of MODFREQDIV factor Reserved MODFREQDIV_MANTISS R/W Set the Mantissa component of MODFREQDIV factor Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 627: Cm_Clksel_Dpll_Mpu Register
DPLL divider factor (0 to 127) (equal to input N of DPLL actual division factor is N+1). SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 628: Cm_Autoidle_Dpll_Ddr Register
Table 8-104. CM_AUTOIDLE_DPLL_DDR Register Field Descriptions Field Type Reset Description 31-3 Reserved AUTO_DPLL_MODE AUTO_DPLL_MODE is not supported. Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 629: Cm_Idlest_Dpll_Ddr Register
0x0 = DPLL_UNLOCKED : DPLL is either in bypass mode or in stop mode. 0x1 = DPLL_LOCKED : DPLL is LOCKED SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 630: Cm_Ssc_Deltamstep_Dpll_Ddr Register
Reserved 19-18 DELTAMSTEP_INTEGER R/W Integer part for DeltaM coefficient 17-0 DELTAMSTEP_FRACTIO R/W Fractional setting for DeltaMStep parameter Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 631: Cm_Ssc_Modfreqdiv_Dpll_Ddr Register
Set the Exponent component of MODFREQDIV factor Reserved MODFREQDIV_MANTISS R/W Set the Mantissa component of MODFREQDIV factor SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 632: Cm_Clksel_Dpll_Ddr Register
DPLL divider factor (0 to 127) (equal to input N of DPLL actual division factor is N+1). Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 633: Cm_Autoidle_Dpll_Disp Register
Table 8-109. CM_AUTOIDLE_DPLL_DISP Register Field Descriptions Field Type Reset Description 31-3 Reserved AUTO_DPLL_MODE AUTO_DPLL_MODE is not supported. SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 634: Cm_Idlest_Dpll_Disp Register
0x0 = DPLL_UNLOCKED : DPLL is either in bypass mode or in stop mode. 0x1 = DPLL_LOCKED : DPLL is LOCKED Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 635: Cm_Ssc_Deltamstep_Dpll_Disp Register
Reserved 19-18 DELTAMSTEP_INTEGER R/W Integer part for DeltaM coefficient 17-0 DELTAMSTEP_FRACTIO R/W Fractional setting for DeltaMStep parameter SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 636: Cm_Ssc_Modfreqdiv_Dpll_Disp Register
Set the Exponent component of MODFREQDIV factor Reserved MODFREQDIV_MANTISS R/W Set the Mantissa component of MODFREQDIV factor Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 637: Cm_Clksel_Dpll_Disp Register
DPLL divider factor (0 to 127) (equal to input N of DPLL actual division factor is N+1). SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 638: Cm_Autoidle_Dpll_Core Register
Table 8-114. CM_AUTOIDLE_DPLL_CORE Register Field Descriptions Field Type Reset Description 31-3 Reserved AUTO_DPLL_MODE This feature is not supported. Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 639: Cm_Idlest_Dpll_Core Register
0x0 = DPLL_UNLOCKED : DPLL is either in bypass mode or in stop mode. 0x1 = DPLL_LOCKED : DPLL is LOCKED SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 640: Cm_Ssc_Deltamstep_Dpll_Core Register
Reserved 19-18 DELTAMSTEP_INTEGER R/W Integer part for DeltaM coefficient 17-0 DELTAMSTEP_FRACTIO R/W Fractional setting for DeltaMStep parameter Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 641: Cm_Ssc_Modfreqdiv_Dpll_Core Register
Set the Exponent component of MODFREQDIV factor Reserved MODFREQDIV_MANTISS R/W Set the Mantissa component of MODFREQDIV factor SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 642: Cm_Clksel_Dpll_Core Register
DPLL divider factor (0 to 127) (equal to input N of DPLL actual division factor is N+1). Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 643: Cm_Autoidle_Dpll_Per Register
Table 8-119. CM_AUTOIDLE_DPLL_PER Register Field Descriptions Field Type Reset Description 31-3 Reserved AUTO_DPLL_MODE AUTO_DPLL_MODE is not supported. SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 644: Cm_Idlest_Dpll_Per Register
0x0 = DPLL_UNLOCKED : DPLL is either in bypass mode or in stop mode. 0x1 = DPLL_LOCKED : DPLL is LOCKED Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 645: Cm_Ssc_Deltamstep_Dpll_Per Register
Reserved 19-18 DELTAMSTEP_INTEGER R/W Integer part for DeltaM coefficient 17-0 DELTAMSTEP_FRACTIO R/W Fractional setting for DeltaMStep parameter SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 646: Cm_Ssc_Modfreqdiv_Dpll_Per Register
Set the Exponent component of MODFREQDIV factor Reserved MODFREQDIV_MANTISS R/W Set the Mantissa component of MODFREQDIV factor Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 647: Cm_Clkdcoldo_Dpll_Per Register
0x1 = CLK_ENABLE : Force this clock to stay enabled even if there is no request Reserved SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 648: Cm_Div_M4_Dpll_Core Register
HSDIVIDER_CLKOUT1_ DPLL post-divider factor, M4, for internal clock generation. Divide values from 1 to 31. Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 649: Cm_Div_M5_Dpll_Core Register
HSDIVIDER_CLKOUT2_ DPLL post-divider factor, M5, for internal clock generation. Divide values from 1 to 31. SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 650: Cm_Clkmode_Dpll_Mpu Register
If disabled, the clock ramping feature is used only during the first lock. Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 651: Cm_Clkmode_Dpll_Mpu Register Field Descriptions
0x6 = DPLL_FR_BYP_MODE : Put the DPLL in Idle Bypass Fast Relock mode. 0x7 = DPLL_LOCK_MODE : Enables the DPLL in Lock mode SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 652: Cm_Clkmode_Dpll_Per Register
Power mode. 0x6 = Reserved6 : Reserved 0x7 = DPLL_LOCK_MODE : Enables the DPLL in Lock mode Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 653: Cm_Clkmode_Dpll_Core Register
If disabled, the clock ramping feature is used only during the first lock. SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 654 0x6 = DPLL_FR_BYP_MODE : Put the DPLL in Idle Bypass Fast Relock mode. 0x7 = DPLL_LOCK_MODE : Enables the DPLL in Lock mode Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 655: Cm_Clkmode_Dpll_Ddr Register
If disabled, the clock ramping feature is used only during the first lock. SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 656: Cm_Clkmode_Dpll_Ddr Register Field Descriptions
0x6 = DPLL_FR_BYP_MODE : Put the DPLL in Idle Bypass Fast Relock mode. 0x7 = DPLL_LOCK_MODE : Enables the DPLL in Lock mode Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 657: Cm_Clkmode_Dpll_Disp Register
If disabled, the clock ramping feature is used only during the first lock. SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 658 0x6 = DPLL_FR_BYP_MODE : Put the DPLL in Idle Bypass Fast Relock mode. 0x7 = DPLL_LOCK_MODE : Enables the DPLL in Lock mode Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 659: Cm_Clksel_Dpll_Periph Register
DPLL divider factor (0 to 255) (equal to input N of DPLL actual division factor is N+1). SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 660: Cm_Div_M2_Dpll_Ddr Register
DPLL_CLKOUT_DIV DPLL M2 post-divider factor (1 to 31). Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 661: Cm_Div_M2_Dpll_Disp Register
DPLL_CLKOUT_DIV DPLL M2 post-divider factor (1 to 31). SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 662: Cm_Div_M2_Dpll_Mpu Register
DPLL_CLKOUT_DIV DPLL M2 post-divider factor (1 to 31). Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 663: Cm_Div_M2_Dpll_Per Register
DPLL_CLKOUT_DIV DPLL M2 post-divider factor (1 to 31). SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 664: Cm_Wkup_Wkup_M3_Clkctrl Register
0x1 = Standby : Module is in standby 17-2 Reserved MODULEMODE Control the way mandatory clocks are managed. Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 665: Cm_Wkup_Uart0_Clkctrl Register
Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen. 0x3 = RESERVED : Reserved SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 666: Cm_Wkup_I2C0_Clkctrl Register
Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen. 0x3 = RESERVED : Reserved Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 667: Cm_Wkup_Adc_Tsc_Clkctrl Register
Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen. 0x3 = RESERVED : Reserved SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 668: Cm_Wkup_Smartreflex0_Clkctrl Register
Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen. 0x3 = RESERVED : Reserved Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 669: Cm_Wkup_Timer1_Clkctrl Register
Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen. 0x3 = RESERVED : Reserved SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 670: Cm_Wkup_Smartreflex1_Clkctrl Register
Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen. 0x3 = RESERVED : Reserved Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 671: Cm_L4_Wkup_Aon_Clkstctrl Register
0x2 = SW_WKUP : Start a software forced wake-up transition on the domain. 0x3 = Reserved : Reserved. SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 672: Cm_Wkup_Wdt1_Clkctrl Register
Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen. 0x3 = RESERVED : Reserved Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 673: Cm_Div_M6_Dpll_Core Register
CM_DPLL. All register offset addresses not listed Table 8-146 should be considered as reserved locations and the register contents should not be modified. SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 674: Cm_Dpll Registers
CLKSEL_GPIO0_DBCLK Selects the Mux select line for GPIO0 debounce clock Section 8.1.12.3.14 [warm reset insensitive] Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 675: Clksel_Timer7_Clk Register
0x1 = SEL2 : Select CLK_M_OSC clock 0x2 = SEL3 : Select CLK_32KHZ clock 0x3 = SEL4 : Reserved SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 676: Clksel_Timer2_Clk Register
0x1 = SEL2 : Select CLK_M_OSC clock 0x2 = SEL3 : Select CLK_32KHZ clock 0x3 = SEL4 : Reserved Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 677: Clksel_Timer3_Clk Register
0x1 = SEL2 : Select CLK_M_OSC clock 0x2 = SEL3 : Select CLK_32KHZ clock 0x3 = SEL4 : Reserved SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 678: Clksel_Timer4_Clk Register
0x1 = SEL2 : Select CLK_M_OSC clock 0x2 = SEL3 : Select CLK_32KHZ clock 0x3 = SEL4 : Reserved Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 679: Cm_Mac_Clksel Register
0x0 = SEL0 : Selects 1/2 divider of SYSCLK2 0x1 = SEL1 : Selects 1/5 divide ratio of SYSCLK2 Reserved SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 680: Clksel_Timer5_Clk Register
0x1 = SEL2 : Select CLK_M_OSC clock 0x2 = SEL3 : Select CLK_32KHZ clock 0x3 = SEL4 : Reserved Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 681: Clksel_Timer6_Clk Register
0x1 = SEL2 : Select CLK_M_OSC clock 0x2 = SEL3 : Select CLK_32KHZ clock 0x3 = SEL4 : Reserved SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 682: Cm_Cpts_Rft_Clksel Register
Selects the Mux select line for cpgmac rft clock [warm reset insensitive] 0x0 = SEL1 : Selects CORE_CLKOUTM5 0x1 = SEL2 : Selects CORE_CLKOUTM4 Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 683: Clksel_Timer1Ms_Clk Register
0x3 = SEL4 : Select CLK_RC32K clock 0x4 = SEL5 : Selects the CLK_32768 from 32KHz Crystal Osc SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 684: Clksel_Gfx_Fclk Register
0x0 = DIV1 : SGX FCLK is same as L3 Clock or 192MHz Clock 0x1 = DIV2 : SGX FCLK is L3 clock/2 or 192Mhz/2 Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 685: Clksel_Pru_Icss_Ocp_Clk Register
0x0 = SEL1 : Select L3F clock as OCP Clock of PRU-ICSS 0x1 = SEL2 : Select DISP DPLL clock as OCP clock of PRU-ICSS SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 686: Clksel_Lcdc_Pixel_Clk Register
0x1 = SEL2 : Select CORE PLL CLKOUTM5 0x2 = SEL3 : Select PER PLL CLKOUTM2 0x3 = SEL4 : Reserved Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 687: Clksel_Wdt1_Clk Register
0x0 = SEL1 : Select 32KHZ clock from RC Oscillator 0x1 = SEL2 : Select 32KHZ from 32K Clock divider SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 688: Clksel_Gpio0_Dbclk Register
It also hold one status bit per clock input of the domain. CM_MPU_MPU_CLKCTRL This register manages the MPU clocks. Section 8.1.12.4.2 Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 689: Cm_Mpu_Clkstctrl Register
0x2 = SW_WKUP : SW_WKUP: Start a software forced wake-up transition on the domain. 0x3 = Reserved : Reserved. SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 690: Cm_Mpu_Mpu_Clkctrl Register
Offset Acronym Register Name Section CM_CLKOUT_CTRL This register provides the control over CLKOUT2 output Section 8.1.12.5.1 690 Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 691 Power, Reset, and Clock Management www.ti.com SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 692: Cm_Clkout_Ctrl Register
CM_RTC. All register offset addresses not listed in Table 8-166 should be considered as reserved locations and the register contents should not be modified. Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 693: Cm_Rtc Registers
ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the domain. SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 694: Cm_Rtc_Rtc_Clkctrl Register
Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen. 0x3 = RESERVED : Reserved Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 695: Cm_Rtc_Clkstctrl Register
CM_GFX. All register offset addresses not listed in Table 8-169 should be considered as reserved locations and the register contents should not be modified. SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 696: Cm_Gfx Registers
This register manages the MMU CFG clocks. Section 8.1.12.7.4 CM_GFX_MMUDATA_CLKCTRL This register manages the MMU clocks. Section 8.1.12.7.5 Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 697: Cm_Gfx_L3_Clkstctrl Register
0x2 = SW_WKUP : SW_WKUP: Start a software forced wake-up transition on the domain. 0x3 = Reserved : Reserved. SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 698: Cm_Gfx_Gfx_Clkctrl Register
Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen. 0x3 = RESERVED : Reserved Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 699: Cm_Gfx_L4Ls_Gfx_Clkstctrl Register
0x2 = SW_WKUP : SW_WKUP: Start a software forced wake-up transition on the domain. 0x3 = Reserved : Reserved. SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 700: Cm_Gfx_Mmucfg_Clkctrl Register
Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen. 0x3 = RESERVED : Reserved Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 701: Cm_Gfx_Mmudata_Clkctrl Register
ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the domain. SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 702 Table 8-175. CM_CEFUSE REGISTERS (continued) Offset Acronym Register Name Section CM_CEFUSE_CEFUSE_CLKCTR This register manages the CEFUSE clocks. Section 8.1.12.8.2 Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 703: Cm_Cefuse_Clkstctrl Register
0x2 = SW_WKUP : SW_WKUP: Start a software forced wake-up transition on the domain. 0x3 = Reserved : Reserved. SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 704: Cm_Cefuse_Cefuse_Clkctrl Register
Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen. 0x3 = RESERVED : Reserved Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 705: Prm_Irq Registers
This register is used to enable and disable events used Section 8.1.13.1.5 to trigger MPU interrupt activation. SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 706: Revision_Prm Register
IP revision [ 7:4] Major revision [ 3:0] Minor revision Examples: 0x10 for 1.0, 0x21 for 2.1 Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 707: Prm_Irqstatus_Mpu Register
Software supervised transition completed event interrupt status (any domain) 0 = IRQ_fal : No interrupt 1 = IRQ_tru : Interrupt is pending Reserved SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 708: Prm_Irqenable_Mpu Register
0 = irq_msk : Interrupt is masked 1 = irq_en : Interrupt is enabled Reserved Reserved Reserved Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 709: Prm_Irqstatus_M3 Register
Software supervised transition completed event interrupt status (any domain) 0 = IRQ_fal : No interrupt 1 = IRQ_tru : Interrupt is pending Reserved SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 710: Prm_Irqenable_M3 Register
0 = irq_msk : Interrupt is masked 1 = irq_en : Interrupt is enabled Reserved Reserved Reserved Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 711: Prm_Per Registers
Section 8.1.13.2.2 domain state. [warm reset insensitive] PM_PER_PWRSTCTRL Controls the power state of PER power domain Section 8.1.13.2.3 SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 712: Rm_Per_Rstctrl Register
0x0 = CLEAR : Reset is cleared for the PRU-ICSS 0x1 = ASSERT : Reset is asserted for the PRU-ICSS Reserved Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 713: Pm_Per_Pwrstst Register
0x0 = OFF : OFF State 0x1 = RET 0x2 = Reserved1 0x3 = ON : ON State SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 714: Pm_Per_Pwrstctrl Register
0x0 = Reserved2 0x1 = Reserved1 0x2 = Reserved : Reserved 0x3 = ON : Memory is ON Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 715: Prm_Wkup Registers
Each bit is set upon release of the domain reset signal. Must be cleared by software. [warm reset insensitive] SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 716: Rm_Wkup_Rstctrl Register
0x0 = CLEAR : Reset is cleared for the M3 0x1 = ASSERT : Reset is asserted for the M3 by A8 Reserved Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 717: Pm_Wkup_Pwrstctrl Register
RETENTION state. 0x1 = logic_ret : Whole logic is retained when domain is in RETENTION state. Reserved Reserved SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 718: Pm_Wkup_Pwrstst Register
0x0 = OFF : Logic in domain is OFF 0x1 = ON : Logic in domain is ON Reserved Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 719: Rm_Wkup_Rstst Register
Each bit is set upon release of the domain reset signal. Must be cleared by software. [warm reset insensitive] SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 720 Power, Reset, and Clock Management www.ti.com Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 721: Pm_Mpu_Pwrstctrl Register
RETENTION state. 0x1 = logic_ret : Whole logic is retained when domain is in RETENTION state. SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 722 0x0 = OFF : OFF State 0x1 = RET 0x2 = Reserved 0x3 = ON : ON State Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 723: Pm_Mpu_Pwrstst Register
0x0 = OFF : OFF State [warm reset insensitive] 0x1 = RET : RET State 0x3 = ON : ON State [warm reset insensitive] SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 724: Rm_Mpu_Rstst Register
Table 8-197. PRM_DEVICE REGISTERS Offset Acronym Register Name Section PRM_RSTCTRL Section 8.1.13.5.1 PRM_RSTTIME Section 8.1.13.5.2 PRM_RSTST Section 8.1.13.5.3 724 Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 725 Register Name Section PRM_SRAM_COUNT Section 8.1.13.5.4 PRM_LDO_SRAM_CORE_SETUP Section 8.1.13.5.5 PRM_LDO_SRAM_CORE_CTRL Section 8.1.13.5.6 PRM_LDO_SRAM_MPU_SETUP Section 8.1.13.5.7 PRM_LDO_SRAM_MPU_CTRL Section 8.1.13.5.8 SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 726: Prm_Rstctrl Register
0x0 = 0x0 : Global warm software reset is cleared. 0x1 = 0x1 : Asserts a global warm software reset. Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 727: Prm_Rsttime Register
(Power domain) reset duration 2 (number of CLK_M_OSC clock cycles) RSTTIME1 (Global) reset duration 1 (number of CLK_M_OSC clock cycles) SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 728: Prm_Rstst Register
Power-on (cold) reset event [warm reset insensitive] 0x0 = 0x0 : No power-on reset. 0x1 = 0x1 : Power-on reset has occurred. Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 729: Prm_Sram_Count Register
Target is 30us. Reserved PCHARGECNT_VALUE Delay between de-assertion of standby_rta_ret_on and standby_rta_ret_good. Counting on system clock. Target is 600ns. SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 730: Prm_Ldo_Sram_Core_Setup Register
0x0 = Short_prot_disabled : Short circuit protection is disabled 0x1 = Short_prot_enabled : Short circuit protection is enabled Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 731 0x0 = RTA_ENABLED : HD memory RTA feature is enabled 0x1 = RTA_DISABLED : HD memory RTA feature is disabled SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 732: Prm_Ldo_Sram_Core_Ctrl Register
0x1 = Enabled : SRAM LDO go to RET mode when all memory of voltage domain are OFF or RET Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 733: Prm_Ldo_Sram_Mpu_Setup Register
0x0 = Short_prot_disabled : Short circuit protection is disabled 0x1 = Short_prot_enabled : Short circuit protection is enabled SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 734 0x0 = RTA_ENABLED : HD memory RTA feature is enabled 0x1 = RTA_DISABLED : HD memory RTA feature is disabled Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 735: Prm_Ldo_Sram_Mpu_Ctrl Register
This register provides a status on the current RTC power Section 8.1.13.6.2 domain state0. [warm reset insensitive] SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 736 Power, Reset, and Clock Management www.ti.com Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 737: Pm_Rtc_Pwrstctrl Register
RETENTION state. 0x1 = logic_ret : Whole logic is retained when domain is in RETENTION state. Reserved SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 738: Pm_Rtc_Pwrstst Register
Each bit is set upon release of the domain reset signal. Must be cleared by software. [warm reset insensitive] 738 Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 739 Power, Reset, and Clock Management www.ti.com SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 740: Pm_Gfx_Pwrstctrl Register
0x0 = OFF : OFF State 0x1 = RET 0x2 = reserved_1 0x3 = ON : ON State Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 741: Rm_Gfx_Rstctrl Register
0x0 = CLEAR : Reset is cleared for the GFX Domain (SGX530) 0x1 = ASSERT : Reset is asserted for the GFX Domain (SGX 530) SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 742: Pm_Gfx_Pwrstst Register
0x0 = OFF : OFF State [warm reset insensitive] 0x1 = RET 0x3 = ON : ON State [warm reset insensitive] Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 743: Rm_Gfx_Rstst Register
This register provides a status on the current CEFUSE Section 8.1.13.8.2 power domain state. [warm reset insensitive] SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 744: Pm_Cefuse_Pwrstctrl Register
0x1 = Reserved : Reserved 0x2 = INACT : INACTIVE state 0x3 = ON : ON State Power, Reset, and Clock Management (PRCM) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 745: Pm_Cefuse_Pwrstst Register
0x1 = RET : Power domain is in RETENTION 0x2 = INACTIVE : Power domain is ON-INACTIVE 0x3 = ON : Power domain is ON-ACTIVE SPRUH73H – October 2011 – Revised April 2013 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 746 Control Module This chapter describes the control module of the device..........................Topic Page ....................Introduction ..................Functional Description ................CONTROL_MODULE Registers Control Module SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 747: Pad Control Register Field Descriptions
Some peripherals do not support slow slew rate. To determine which interfaces support each slew rate, see AM335x ARM Cortex-A8 Microprocessors (MPUs) (literature number SPRS717). SPRUH73H – October 2011 – Revised April 2013 Control Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 748: Mode Selection
Module to select the event to be routed to the TPCC. Direct mapped event is the default (mux selection set to ‘0’). Control Module SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 749: Event Crossbar
TX Event from Cortex M3 to Cortex A8 MPU Subsystem. See the M3_TXEV_EOI register description for further detail. SPRUH73H – October 2011 – Revised April 2013 Control Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 750: Interconnect Priority Values
Outputs a charger enable signal (3.3 V level active high CMOS driver) when a charger is present. • Allows you to enable/disable the circuitry to save power Control Module SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 751: Usb Charger Detection
The charger detection circuitry performs the following steps of the Battery Charging specification v1.1: 1. VBUS Detect 2. Data Contact Detect SPRUH73H – October 2011 – Revised April 2013 Control Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 752: Gmii_Sel Register
CONF_MII1_CRS • CONF_MII1_RX_ER • CONF_MII1_TX_EN • CONF_MII1_RX_DV • CONF_MII1_TXD[3:0] • CONF_MII1_TX_CLK • CONF_MII1_RX_CLK • CONF_MII1_RXD[3:0] • CONF_RMII1_REF_CLK • CONF_MDIO_DATA • CONF_MDIO_CLK Control Module SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 753: Available Sources For Timer[5-7] And Ecap[0-2] Events
GPIO 2 GPIOINT2B GPIO 3 GPIOINT3A GPIO 3 GPIOINT3B DCAN0 DCAN0_INT0 DCAN0 DCAN0_INT1 DCAN0 DCAN0_PARITY DCAN1 DCAN1_INT0 DCAN1 DCAN1_INT1 DCAN1 DCAN1_PARITY SPRUH73H – October 2011 – Revised April 2013 Control Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 754 Functional Description www.ti.com Control Module SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 755: Timer Events
ADC External event selected PRU-ICSS Host Event 0 Timer 4 Event Timer 5 Event Timer 6 Event Timer 7 Event 101-111 Reserved SPRUH73H – October 2011 – Revised April 2013 Control Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 756: Ddr Slew Rate Control Settings
Unconn ddr_d15 ddr_d7 ddr_a8 ddr_a11 ddr_a1 ddr_dqm1 ddr_dqm0 756 Control Module SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 757: Control_Module Registers
Section 9.3.30 650h gmii_sel Section 9.3.31 664h pwmss_ctrl Section 9.3.32 670h mreqprio_0 Section 9.3.33 674h mreqprio_1 Section 9.3.34 690h hw_event_sel_grp1 Section 9.3.35 SPRUH73H – October 2011 – Revised April 2013 Control Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 758 864h conf_gpmc_a9 Section 9.3.51 868h conf_gpmc_a10 Section 9.3.51 86Ch conf_gpmc_a11 Section 9.3.51 870h conf_gpmc_wait0 Section 9.3.51 874h conf_gpmc_wpn Section 9.3.51 758 Control Module SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 759 Section 9.3.51 920h conf_mii1_txd2 Section 9.3.51 924h conf_mii1_txd1 Section 9.3.51 928h conf_mii1_txd0 Section 9.3.51 92Ch conf_mii1_tx_clk Section 9.3.51 930h conf_mii1_rx_clk Section 9.3.51 SPRUH73H – October 2011 – Revised April 2013 Control Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 760 9F8h conf_rtc_pwronrstn Section 9.3.51 9FCh conf_pmic_power_en Section 9.3.51 A00h conf_ext_wakeup Section 9.3.51 A04h conf_rtc_kaldo_enn Section 9.3.51 A1Ch conf_usb0_drvvbus Section 9.3.51 760 Control Module SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 761 Section 9.3.87 1404h ddr_cmd0_ioctrl Section 9.3.88 1408h ddr_cmd1_ioctrl Section 9.3.89 140Ch ddr_cmd2_ioctrl Section 9.3.90 1440h ddr_data0_ioctrl Section 9.3.91 1444h ddr_data1_ioctrl Section 9.3.92 SPRUH73H – October 2011 – Revised April 2013 Control Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 762: Control_Revision Register
Chip Support Library (CSL) / Drivers 00: Non custom (standard) revision ip_rev_minor Minor Revision (Y). Control Module SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 763: Control_Hwinfo Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 9-12. control_hwinfo Register Field Descriptions Field Type Reset Description 31-0 ip_hwinfo IP Module dependent SPRUH73H – October 2011 – Revised April 2013 Control Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 764: Control_Sysconfig Register
Sensitivity to Emulation suspend input. 0: Module is sensitive to EMU suspend 1: Module not sensitive to EMU suspend Reserved Control Module SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 765: Control_Status Register
011: General Purpose (GP) Device 111: Reserved sysboot0 Selected boot mode. See SYSBOOT Configuration Pins for more information. Reset value is from SYSBOOT[7:0]. SPRUH73H – October 2011 – Revised April 2013 Control Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 766: Control_Emif_Sdram_Config Register
All other values are reserved. DDR2_DDQS DDR2 differential DQS enable. Set to 0 for single ended DQS. Set to 1 for differential DQS Control Module SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 767 (9 column bits), set to 2 for 1024-word page (10 column bits), and set to 3 for 2048-word page (11 column bits). All other values are reserved. SPRUH73H – October 2011 – Revised April 2013 Control Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 768: Core_Sldo_Ctrl Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 9-16. core_sldo_ctrl Register Field Descriptions Field Type Reset Description 31-26 Reserved 25-16 vset Trims VDDAR 15-0 Reserved Control Module SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 769: Mpu_Sldo_Ctrl Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 9-17. mpu_sldo_ctrl Register Field Descriptions Field Type Reset Description 31-26 Reserved 25-16 vset Trims VDDAR 15-0 Reserved SPRUH73H – October 2011 – Revised April 2013 Control Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 770: Clk32Kdivratio_Ctrl Register
0 : OPP100 operation, use ratio for 24MHz to 32KHz division 1 : OPP50 operation, use ratio for 12MHz to 32KHz division Control Module SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 771: Bandgap_Ctrl Register
ADC end of conversion 0: End of conversion 1: Conversion in progress tshut 0: Normal operation 1: Thermal shutdown event (greater than 147C) SPRUH73H – October 2011 – Revised April 2013 Control Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 772: Bandgap_Trim Register
23-16 dtrbgapv trim the output voltage of bandgap 15-8 dtrtemps trim the temperature sensor dtrtempsc trim the temperature sensor Control Module SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 773: Pll_Clkinpulow_Ctrl Register
1 : Select PER_CLKOUT_M2 clock as CLKINPULOW mpu_dpll_clkinpulow_sel 0 : Select CORE_CLKOUT_M6 clock as CLKINPULOW 1 : Select PER_CLKOUT_M2 clock as CLKINPULOW SPRUH73H – October 2011 – Revised April 2013 Control Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 774: Mosc_Ctrl Register
0: 1-MHz ohm resistor is connected between padxi and padxo for oscillator bias 1: Internal resistor is disconnected Control Module SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 775: Deepsleep_Ctrl Register
1: Master oscillator output is gated Reserved 15-0 dscount Programmable count of how many CLK_M_OSC clocks needs to be seen before exiting deep sleep mode SPRUH73H – October 2011 – Revised April 2013 Control Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 776: Dpll_Pwr_Sw_Status Register
Power Good status for PER DPLL 0: Power Fault 1: Power Good ponout_per Power Enable status for PER DPLL 0: Disabled 1: Enabled Reserved Control Module SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 777: Device_Id Register
Reset value is revision-dependent. 27-12 partnum B944h Device part number (unique JTAG ID) 11-1 mfgr 017h Manufacturer's JTAG ID Reserved SPRUH73H – October 2011 – Revised April 2013 Control Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 778: Dev_Feature Register
1: CP Switch IP (Ethernet) is enabled Reset value is device-dependent. pru_icss 0: PRU-ICSS is disabled 1: PRU-ICSS is enabled Reset value is device-dependent. Control Module SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 779: Init_Priority_0 Register
P1500 Port Initiator priority 13-8 Reserved System MMU initiator priority pru_icss PRU-ICSS initiator priority Reserved host_arm Host Cortex A8 initiator priority SPRUH73H – October 2011 – Revised April 2013 Control Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 780: Init_Priority_1 Register
17-16 Reserved 15-8 Reserved usb_qmgr USB Queue Manager initiator priority usb_dma USB DMA port initiator priority Reserved cpsw CPSW initiator priority Control Module SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 781: Mmu_Cfg Register
This bit defaults to enabled but an identical bit within an MMU configuration register defaults to disabled and must be set after the page tables are programmed for MMU operation. Reserved SPRUH73H – October 2011 – Revised April 2013 Control Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 782: Tptc_Cfg Register
10: 64 byte 11: 128 byte tc0dbs TPTC0 Default Burst Size 00: 16 byte 01: 32 byte 10: 64 byte 11: 128 byte Control Module SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 783: Usb_Ctrl0 Register
0: Charger detection on 1: Charger detection is bypassed dppullup Pullup on DP line 0: No effect 1: Enable pullup on DP line SPRUH73H – October 2011 – Revised April 2013 Control Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 784 0: PHY in normal mode 1: PHY Powered down cm_pwrdn Power down the USB CM PHY 0: PHY in normal mode 1: PHY Powered down Control Module SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 785: Usb_Sts0 Register
Charger Comparator Output chgdetect Charger Detection Status 0: Charger was no detected 1: Charger was detected chgdetdone Charger Detection Protocol Done SPRUH73H – October 2011 – Revised April 2013 Control Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 786: Usb_Ctrl1 Register
0: Charger detection on 1: Charger detection is bypassed dppullup Pullup on DP line 0: No effect 1: Enable pullup on DP line Control Module SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 787 0: PHY in normal mode 1: PHY Powered down cm_pwrdn Power down the USB CM PHY 1: PHY Powered down 0: PHY in normal mode SPRUH73H – October 2011 – Revised April 2013 Control Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 788: Usb_Sts1 Register
Charger Comparator Output chgdetect Charger Detection Status 0: Charger was no detected 1: Charger was detected chgdetdone Charger Detection Protocol Done Control Module SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 789: Mac_Id0_Lo Register
15-8 macaddr_7_0 MAC0 Address - Byte 0 Reset value is device-dependent. macaddr_15_8 MAC0 Address - Byte 1 Reset value is device-dependent. SPRUH73H – October 2011 – Revised April 2013 Control Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 790: Mac_Id0_Hi Register
15-8 macaddr_39_32 MAC0 Address - Byte 4 Reset value is device-dependent. macaddr_47_40 MAC0 Address - Byte 5 Reset value is device-dependent. Control Module SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 791: Mac_Id1_Lo Register
15-8 macaddr_7_0 MAC1 Address - Byte 0 Reset value is device-dependent. macaddr_15_8 MAC1 Address - Byte 1 Reset value is device-dependent. SPRUH73H – October 2011 – Revised April 2013 Control Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 792: Mac_Id1_Hi Register
15-8 macaddr_39_32 MAC1 Address - Byte 4 Reset value is device-dependent. macaddr_47_40 MAC1 Address - Byte 5 Reset value is device-dependent. Control Module SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 793: Dcan_Raminit Register
A transition from 0 to 1 will start DCAN1 RAM initialization sequence. dcan0_raminit_start A transition from 0 to 1 will start DCAN0 RAM initialization sequence. SPRUH73H – October 2011 – Revised April 2013 Control Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 794: Usb_Wkup_Ctrl Register
Write to 1 enables WKUP from USB PHY1 Reserved phy0_wuen PHY0 Wakeup Enable. Write to 1 enables WKUP from USB PHY0 Control Module SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 795: Gmii_Sel Register Field Descriptions
10: Port2 RGMII Mode 11: Not Used gmii1_sel 00: Port1 GMII/MII Mode 01: Port1 RMII Mode 10: Port1 RGMII Mode 11: Not Used SPRUH73H – October 2011 – Revised April 2013 Control Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 796: Pwmss_Ctrl Register
Description 31-3 Reserved pwmss2_tbclken Timebase clock enable for PWMSS2 pwmss1_tbclken Timebase clock enable for PWMSS1 pwmss0_tbclken Timebase clock enable for PWMSS0 Control Module SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 797: Mreqprio_0 Register
MReqPriority for PRU-ICSS PRU0 Initiator OCP Interface Reserved sab_init1 MReqPriority for MPU Initiator 1 OCP Interface Reserved sab_init0 MReqPriority for MPU Initiator 0 OCP Interface SPRUH73H – October 2011 – Revised April 2013 Control Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 798: Mreqprio_1 Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 9-44. mreqprio_1 Register Field Descriptions Field Type Reset Description 31-3 Reserved MReqPriority for Expansion Initiator OCP Interface Control Module SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 799: Hw_Event_Sel_Grp1 Register
Select 3rd trace event from group 1 15-8 event2 Select 2nd trace event from group 1 event1 Select 1st trace event from group 1 SPRUH73H – October 2011 – Revised April 2013 Control Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 800: Hw_Event_Sel_Grp2 Register
Select 7th trace event from group 2 15-8 event6 Select 6th trace event from group 2 event5 Select 5th trace event from group 2 Control Module SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 801: Hw_Event_Sel_Grp3 Register
Select 11th trace event from group 3 15-8 event10 Select 10th trace event from group 3 event9 Select 9th trace event from group 3 SPRUH73H – October 2011 – Revised April 2013 Control Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 802: Hw_Event_Sel_Grp4 Register
Select 15th trace event from group 4 15-8 event14 Select 14th trace event from group 4 event13 Select 13th trace event from group 4 Control Module SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 803: Smrt_Ctrl Register
1: Enable sensor (SRSLEEP on sensor driven to 0). sr0_sleep 0: Disable sensor (SRSLEEP on sensor driven to 1) 1: Enable sensor (SRSLEEP on sensor driven to 0). SPRUH73H – October 2011 – Revised April 2013 Control Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 804: Mpuss_Hw_Debug_Sel Register
0001: Group 1 0010: Group 2 0011: Group 3 0100: Group 4 0101: Group 5 0110: Group 6 0111: Group 7 1xxx: Reserved Control Module SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 805: Mpuss_Hw_Dbg_Info Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 9-51. mpuss_hw_dbg_info Register Field Descriptions Field Type Reset Description 31-0 hw_dbg_info Hardware Debug Info from MPU. SPRUH73H – October 2011 – Revised April 2013 Control Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 806: Vdd_Mpu_Opp_050 Register
Table 9-52. vdd_mpu_opp_050 Register Field Descriptions Field Type Reset Description 31-24 Reserved 23-0 ntarget Ntarget value for MPU Voltage domain OPP50 Reset value is device-dependent. Control Module SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 807: Vdd_Mpu_Opp_100 Register
Table 9-53. vdd_mpu_opp_100 Register Field Descriptions Field Type Reset Description 31-24 Reserved 23-0 ntarget Ntarget value for MPU Voltage domain OPP100 Reset value is device-dependent. SPRUH73H – October 2011 – Revised April 2013 Control Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 808: Vdd_Mpu_Opp_120 Register
Table 9-54. vdd_mpu_opp_120 Register Field Descriptions Field Type Reset Description 31-24 Reserved 23-0 ntarget Ntarget value for MPU Voltage domain OPP120 Reset value is device-dependent. Control Module SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 809: Vdd_Mpu_Opp_Turbo Register
Table 9-55. vdd_mpu_opp_turbo Register Field Descriptions Field Type Reset Description 31-24 Reserved 23-0 ntarget Ntarget value for MPU Voltage domain OPPTURBO Reset value is device-dependent. SPRUH73H – October 2011 – Revised April 2013 Control Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 810: Vdd_Core_Opp_050 Register
Table 9-56. vdd_core_opp_050 Register Field Descriptions Field Type Reset Description 31-24 Reserved 23-0 ntarget Ntarget value for CORE Voltage domain OPP50 Reset value is device-dependent. Control Module SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 811: Vdd_Core_Opp_100 Register
Table 9-57. vdd_core_opp_100 Register Field Descriptions Field Type Reset Description 31-24 Reserved 23-0 ntarget Ntarget value for CORE Voltage domain OPP100 Reset value is device-dependent. SPRUH73H – October 2011 – Revised April 2013 Control Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 812: Bb_Scale Register
Field Type Reset Description 31-12 Reserved 11-8 scale Dynamic core voltage scaling for class 0 Reserved bbias BBIAS value from Efuse Control Module SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 813: Usb_Vid_Pid Register
Table 9-59. usb_vid_pid Register Field Descriptions Field Type Reset Description 31-16 usb_vid 0x451 USB Vendor ID 15-0 usb_pid 0x6141 USB Product ID SPRUH73H – October 2011 – Revised April 2013 Control Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 814: Efuse_Sma Register
0x1FDF - 300 MHz ARM MPU Maximum (ZCE Package only) 0x1F9F - 600 MHz ARM MPU Maximum (ZCE Package only) All other values are reserved. Control Module SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 815: Conf__ Register
0: Pullup/pulldown enabled 1: Pullup/pulldown disabled Reset value is pad-dependent. conf_<module>_<pin>_m Pad functional signal mux select. mode Reset value is pad-dependent. SPRUH73H – October 2011 – Revised April 2013 Control Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 816: Cqdetect_Status Register
1: IOs are 3.3V mode 0: IOs are 1.8V mode cqstat_gpmc 1: IOs are 3.3V mode 0: IOs are 1.8V mode Control Module SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 817: Ddr_Io_Ctrl Register
1 = clock is synchronously gated Reserved mddr_sel 0: IOs set for DDR2/DDR3 (STL mode) 1: IOs set for mDDR (CMOS mode) 27-0 Reserved SPRUH73H – October 2011 – Revised April 2013 Control Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 818: Vtp_Ctrl Register
110: Update on seven consecutive update requests 111: Update on eight consecutive update requests clrz clears flops, start count again, after low going pulse Control Module SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 819: Vref_Ctrl Register
11 : Pad/Bias2 connected to internal reference VDDS/2 for 8uA current load ddr_vref_en active high internal reference enable for DDR SPRUH73H – October 2011 – Revised April 2013 Control Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 820: Tpcc_Evt_Mux_0_3 Register
Selects 1 of 64 inputs for DMA event 1 Reserved evt_mux_0 Selects 1 of 64 inputs for DMA event 0 Control Module SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 821: Tpcc_Evt_Mux_4_7 Register
Selects 1 of 64 inputs for DMA event 5 Reserved evt_mux_4 Selects 1 of 64 inputs for DMA event 4 SPRUH73H – October 2011 – Revised April 2013 Control Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 822: Tpcc_Evt_Mux_8_11 Register
Selects 1 of 64 inputs for DMA event 9 Reserved evt_mux_8 Selects 1 of 64 inputs for DMA event 8 Control Module SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 823: Tpcc_Evt_Mux_12_15 Register
Selects 1 of 64 inputs for DMA event 13 Reserved evt_mux_12 Selects 1 of 64 inputs for DMA event 12 SPRUH73H – October 2011 – Revised April 2013 Control Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 824: Tpcc_Evt_Mux_16_19 Register
Selects 1 of 64 inputs for DMA event 17 Reserved evt_mux_16 Selects 1 of 64 inputs for DMA event 16 Control Module SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 825: Tpcc_Evt_Mux_20_23 Register
Selects 1 of 64 inputs for DMA event 21 Reserved evt_mux_20 Selects 1 of 64 inputs for DMA event 20 SPRUH73H – October 2011 – Revised April 2013 Control Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 826: Tpcc_Evt_Mux_24_27 Register
Selects 1 of 64 inputs for DMA event 25 Reserved evt_mux_24 Selects 1 of 64 inputs for DMA event 24 Control Module SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 827: Tpcc_Evt_Mux_28_31 Register
Selects 1 of 64 inputs for DMA event 29 Reserved evt_mux_28 Selects 1 of 64 inputs for DMA event 28 SPRUH73H – October 2011 – Revised April 2013 Control Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 828: Tpcc_Evt_Mux_32_35 Register
Selects 1 of 64 inputs for DMA event 33 Reserved evt_mux_32 Selects 1 of 64 inputs for DMA event 32 Control Module SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 829: Tpcc_Evt_Mux_36_39 Register
Selects 1 of 64 inputs for DMA event 37 Reserved evt_mux_36 Selects 1 of 64 inputs for DMA event 36 SPRUH73H – October 2011 – Revised April 2013 Control Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 830: Tpcc_Evt_Mux_40_43 Register
Selects 1 of 64 inputs for DMA event 41 Reserved evt_mux_40 Selects 1 of 64 inputs for DMA event 40 Control Module SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 831: Tpcc_Evt_Mux_44_47 Register
Selects 1 of 64 inputs for DMA event 45 Reserved evt_mux_44 Selects 1 of 64 inputs for DMA event 44 SPRUH73H – October 2011 – Revised April 2013 Control Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 832: Tpcc_Evt_Mux_48_51 Register
Selects 1 of 64 inputs for DMA event 49 Reserved evt_mux_48 Selects 1 of 64 inputs for DMA event 48 Control Module SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 833: Tpcc_Evt_Mux_52_55 Register
Selects 1 of 64 inputs for DMA event 53 Reserved evt_mux_52 Selects 1 of 64 inputs for DMA event 52 SPRUH73H – October 2011 – Revised April 2013 Control Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 834: Tpcc_Evt_Mux_56_59 Register
Selects 1 of 64 inputs for DMA event 57 Reserved evt_mux_56 Selects 1 of 64 inputs for DMA event 56 Control Module SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 835: Tpcc_Evt_Mux_60_63 Register
Selects 1 of 64 inputs for DMA event 61 Reserved evt_mux_60 Selects 1 of 64 inputs for DMA event 60 SPRUH73H – October 2011 – Revised April 2013 Control Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 836: Timer_Evt_Capt Register
Timer 7 event capture mux 15-13 Reserved 12-8 timer6_evtcapt Timer 6 event capture mux Reserved timer5_evtcapt Timer 5 event capture mux Control Module SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 837: Ecap_Evt_Capt Register
Reserved 20-16 ecap2_evtcapt ECAP2 event capture mux 15-13 Reserved 12-8 ecap1_evtcapt ECAP1 event capture mux Reserved ecap0_evtcapt ECAP0 event capture mux SPRUH73H – October 2011 – Revised April 2013 Control Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 838: Adc_Evt_Capt Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 9-84. adc_evt_capt Register Field Descriptions Field Type Reset Description 31-4 Reserved adc_evtcapt ECAP0 event capture mux Control Module SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 839: Reset_Iso Register
Table 9-85. reset_iso Register Field Descriptions Field Type Reset Description 31-1 Reserved iso_control 0 : Ethernet Switch is not isolated 1 : Ethernet Switch is isolated SPRUH73H – October 2011 – Revised April 2013 Control Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 840: Dpll_Pwr_Sw_Ctrl Register
1: Controlled by corresponding bits in this register. Reserved isoscan_disp Drives ISOSCAN of DISP PLL. ret_disp Drives RET of DISP DPLL. reset_disp Drives RESET of DISP DPLL. Control Module SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 841 Drives ISO signal of PER DPLL. pgoodin_per Drives PGOODIN signal of PER DPLL. ponin_per Drives PONIN signal of PER DPLL. Reserved SPRUH73H – October 2011 – Revised April 2013 Control Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 842: Ddr_Cke_Ctrl Register
0: CKE to memories gated off to zero. External DRAM memories will not able to register DDR commands from device 1: Normal operation. CKE is now controlled by EMIF/DDR PHY. Control Module SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 843: Sma2 Register
1: Allows hardware to bring VSLDO out of retention on wakeup from deep-sleep. rmii2_crs_dv_mode_sel 0: Select MMC2_DAT7 on GPMC_A9 pin in MODE3. 1: Select RMII2_CRS_DV on GPMC_A9 pin in MODE3. SPRUH73H – October 2011 – Revised April 2013 Control Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 844: M3_Txev_Eoi Register
This bit is sticky and for re-arming the IRQ[78], S/W must write a 0 to this field in the ISR Control Module SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 845: Ipc_Msg_Reg0 Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 9-90. ipc_msg_reg0 Register Field Descriptions Field Type Reset Description 31-0 ipc_msg_reg0 Inter Processor Messaging Register SPRUH73H – October 2011 – Revised April 2013 Control Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 846: Ipc_Msg_Reg1 Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 9-91. ipc_msg_reg1 Register Field Descriptions Field Type Reset Description 31-0 ipc_msg_reg1 Inter Processor Messaging Register Control Module SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 847: Ipc_Msg_Reg2 Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 9-92. ipc_msg_reg2 Register Field Descriptions Field Type Reset Description 31-0 ipc_msg_reg2 Inter Processor Messaging Register SPRUH73H – October 2011 – Revised April 2013 Control Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 848: Ipc_Msg_Reg3 Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 9-93. ipc_msg_reg3 Register Field Descriptions Field Type Reset Description 31-0 ipc_msg_reg3 Inter Processor Messaging Register Control Module SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 849: Ipc_Msg_Reg4 Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 9-94. ipc_msg_reg4 Register Field Descriptions Field Type Reset Description 31-0 ipc_msg_reg4 Inter Processor Messaging Register SPRUH73H – October 2011 – Revised April 2013 Control Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 850: Ipc_Msg_Reg5 Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 9-95. ipc_msg_reg5 Register Field Descriptions Field Type Reset Description 31-0 ipc_msg_reg5 Inter Processor Messaging Register Control Module SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 851: Ipc_Msg_Reg6 Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 9-96. ipc_msg_reg6 Register Field Descriptions Field Type Reset Description 31-0 ipc_msg_reg6 Inter Processor Messaging Register SPRUH73H – October 2011 – Revised April 2013 Control Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 852: Ipc_Msg_Reg7 Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 9-97. ipc_msg_reg7 Register Field Descriptions Field Type Reset Description 31-0 ipc_msg_reg7 Inter Processor Messaging Register Control Module SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 853: Ddr_Cmd0_Ioctrl Register
See the DDR Slew Rate Control Settings table in the Control Module Functional Description section for a definition of these bits. SPRUH73H – October 2011 – Revised April 2013 Control Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 854 These connect as I2, I1, I0 to the corresponding DDR IO buffer. See the DDR Impedance Control Settings table in the Control Module Functional Description section for a definition of these bits. Control Module SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 855: Ddr_Cmd1_Ioctrl Register
See the DDR Slew Rate Control Settings table in the Control Module Functional Description section for a definition of these bits. SPRUH73H – October 2011 – Revised April 2013 Control Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 856 These connect as I2, I1, I0 to the corresponding DDR IO buffer. See the DDR Impedance Control Settings table in the Control Module Functional Description section for a definition of these bits. Control Module SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 857: Ddr_Cmd2_Ioctrl Register
See the DDR Slew Rate Control Settings table in the Control Module Functional Description section for a definition of these bits. SPRUH73H – October 2011 – Revised April 2013 Control Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 858 These connect as I2, I1, I0 to the corresponding DDR IO buffer. See the DDR Impedance Control Settings table in the Control Module Functional Description section for a definition of these bits. Control Module SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 859: Ddr_Data0_Ioctrl Register
Functional Description section for a mapping of macro bits to I/Os. WD1:WD0 00: Pullup/Pulldown disabled 01: Weak pullup enabled 10: Weak pulldown enabled 11: Weak keeper enabled SPRUH73H – October 2011 – Revised April 2013 Control Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 860 These connect as I2, I1, I0 of the corresponding IO buffer. See the DDR Impedance Control Settings table in the Control Module Functional Description section for a definition of these bits. Control Module SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 861: Ddr_Data1_Ioctrl Register
Functional Description section for a mapping of macro bits to I/Os. WD1:WD0 00: Pullup/Pulldown disabled 01: Weak pullup enabled 10: Weak pulldown enabled 11: Weak keeper enabled SPRUH73H – October 2011 – Revised April 2013 Control Module Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 862 These connect as I2, I1, I0 of the corresponding IO buffer. See the DDR Impedance Control Settings table in the Control Module Functional Description section for a definition of these bits. Control Module SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 863 SPRUH73H – October 2011 – Revised April 2013 Interconnects This chapter describes the interconnects of the device..........................Topic Page ....................10.1 Introduction SPRUH73H – October 2011 – Revised April 2013 Interconnects Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 864 10-1. Arrows indicate the master/slave relationship not data flow. L3 is partitioned into two separate clock domains: L3F corresponds to L3 Fast clock domain and L3S corresponds to L3 Slow clock domain. Interconnects SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 865: L3 Topology
– L4_FAST 32-bit target port • – 4 L4_PER peripheral 32-bit target ports – GPMC 32-bit target port – McASP0 32-bit target port SPRUH73H – October 2011 – Revised April 2013 Interconnects Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 866: L3 Master - Slave Connectivity
0x0E PRU-ICSS (PRU0) 0x0F PRU-ICSS (PRU1) 0x30 GEMAC 0x20 SGX530 0x34 USB0 DMA 0x35 USB1 Queue Mgr 0x04 EMU (DAP) 0x05 IEEE1500 Interconnects SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 867: Mconnid Assignment
STM (similar to a printf()). HW indicates debug data captured automatically by hardware. A '0' entry indicates no debug capability. SPRUH73H – October 2011 – Revised April 2013 Interconnects Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 868: L4 Topology
Spinlock SmartReflex 1 eCAP/eQEP/ePWM2 UART1 UART0 eFuse Ctl UART2 WDT1 UART3 GPIO1 UART4 GPIO2 UART5 GPIO3 DebugSS I2C1 PRCM HWMaster1 I2C2 IEEE1500 Interconnects SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 869 11.1 Introduction ...................... 11.2 Integration ..................11.3 Functional Description ..................... 11.4 EDMA3 Registers ....................11.5 Appendix A 1018 SPRUH73H – October 2011 – Revised April 2013 Enhanced Direct Memory Access (EDMA) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 870: Edma3 Controller Block Diagram
Chain Synchronization (completion of one transfer chains to the next) – Parameterizable support for programmable DMA Channel to PaRAM mapping Enhanced Direct Memory Access (EDMA) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 871 Programmable Priority levels (up to 8) • Background programmation capability • Supports 2-dimensional transfers with independent indexes on Source and Destination. SPRUH73H – October 2011 – Revised April 2013 Enhanced Direct Memory Access (EDMA) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 872 Single clock domain for all interfaces 11.1.3.2 Unsupported TPTC Features There are no unsupported TPTC features on this device. Enhanced Direct Memory Access (EDMA) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 873: Tpcc Integration
Clock Signal Max Freq Reference / Source Comments tpcc_clk_pi 200 MHz CORE_CLKOUTM4 pd_per_l3_gclk Interface / Functional clock From PRCM SPRUH73H – October 2011 – Revised April 2013 Enhanced Direct Memory Access (EDMA) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 874: Tptc Integration
Max Freq Reference / Source Comments tptc_clk_pi 200 MHz CORE_CLKOUTM4 pd_per_l3_gclk Interface / Functional clock From PRCM 874 Enhanced Direct Memory Access (EDMA) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 875 Integration www.ti.com 11.2.2.3 TPTC Pin List The TPTC module does not include any external interface pins. SPRUH73H – October 2011 – Revised April 2013 Enhanced Direct Memory Access (EDMA) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 876 DMA channel from a QDMA channel is the method that the system uses to trigger transfers. See Section 11.3.4. Enhanced Direct Memory Access (EDMA) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 877: Edma3 Channel Controller (Edma3Cc) Block Diagram
DMA channels being higher priority events than the QDMA channels. Among the two groups of channels, the lowest-numbered channel is the highest priority. SPRUH73H – October 2011 – Revised April 2013 Enhanced Direct Memory Access (EDMA) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 878: Edma3 Transfer Controller (Edma3Tc) Block Diagram
(also, see Section 11.3.1.1 for more information on transfer completion reporting). Enhanced Direct Memory Access (EDMA) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 879: Definition Of Acnt, Bcnt, And Ccnt
CCNT frames in Block/3rd dimmension Frame CCNT Array 1 Array 2 Array BCNT BCNT arrays in Frame/2nd dimmension SPRUH73H – October 2011 – Revised April 2013 Enhanced Direct Memory Access (EDMA) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 880: A-Synchronized Transfers (Acnt = N, Bcnt = 4, Ccnt = 3)
(SRC|DST) CIDX (SRC|DST) (SRC|DST) (SRC|DST) BIDX BIDX BIDX Frame 2 Array 0 Array 1 Array 2 Array 3 Enhanced Direct Memory Access (EDMA) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 881: Ab-Synchronized Transfers (Acnt = N, Bcnt = 4, Ccnt = 3)
64 channels that are direct mapped and can be used as link or QDMA sets if not used for DMA channels • 64 channels remain for link or QDMA sets SPRUH73H – October 2011 – Revised April 2013 Enhanced Direct Memory Access (EDMA) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 882: Edma3 Parameter Ram Contents
Each parameter set of PaRAM is organized into eight 32-bit words or 32 bytes, as shown in Figure 11-9 and described in Table 11-6. Each PaRAM set consists of 16-bit and 32-bit parameters. Enhanced Direct Memory Access (EDMA) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 883: Param Set
CCNT +1Ch EDMA Base Address + 5FC0 Parameter set 254 EDMA Base Address + 5FE0 Parameter set 255 SPRUH73H – October 2011 – Revised April 2013 Enhanced Direct Memory Access (EDMA) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 884: Edma3 Channel Parameter Description
It is recommended to access the parameter set sets as 32-bit words whenever possible. Enhanced Direct Memory Access (EDMA) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 885: Channel Options Parameter (Opt)
Reserved. Always write 0 to this bit; writes of 1 to this bit are not supported and attempts to do so may result in undefined behavior. SPRUH73H – October 2011 – Revised April 2013 Enhanced Direct Memory Access (EDMA) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 886 LSBs of address must be 0). The EDMA3TC will signal an error, if this rule is violated. See Section 11.3.12.3 for additional details. Enhanced Direct Memory Access (EDMA) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 887 It applies to both A-synchronized and AB-synchronized transfers. See SRCBIDX for examples. SPRUH73H – October 2011 – Revised April 2013 Enhanced Direct Memory Access (EDMA) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 888 A dummy PaRAM set is defined as a PaRAM set where at least one of the count fields (ACNT, BCNT, or CCNT) is cleared to 0 and at least one of the count fields is nonzero. Enhanced Direct Memory Access (EDMA) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 889: Dummy And Null Transfer Request
A-synchronized: ACNT, BCNTRLD, SRCBIDX, DSTBIDX, SRCCIDX, DSTCIDX, OPT, LINK. • AB-synchronized: ACNT, BCNT, BCNTRLD, SRCBIDX, DSTBIDX, SRCCIDX, DSTCIDX, OPT, LINK. SPRUH73H – October 2011 – Revised April 2013 Enhanced Direct Memory Access (EDMA) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 890: Parameter Updates In Edma3Cc (For Non-Null, Non-Dummy Param Set)
You should ensure that no transfer is allowed to cross internal port boundaries between peripherals. A single TR must target a single source/destination slave endpoint. Enhanced Direct Memory Access (EDMA) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 891 (INCR) mode (SAM/DAM =0) by appropriately programming the count and indices values. SPRUH73H – October 2011 – Revised April 2013 Enhanced Direct Memory Access (EDMA) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 892: Linked Transfer
Parameter set 3 Link=FFFFh EDMA Base Address + 5FC0h Parameter set 254 EDMA Base Address + 5FE0h Parameter set 255 Enhanced Direct Memory Access (EDMA) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 893: Link-To-Self Transfer
• Manually-triggered transfer request:The CPU to manually triggers a transfer by writing a 1 to the SPRUH73H – October 2011 – Revised April 2013 Enhanced Direct Memory Access (EDMA) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 894 (ESR.En = 0), then the second event is registered as a missed event in the corresponding bit of the event missed register (EMR.En = 1). Enhanced Direct Memory Access (EDMA) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 895 CPU(s) with a minimum number of linear writes to PaRAM. Link triggering allows a linked list of transfers to be executed, using a single QDMA PaRAM set and multiple link PaRAM sets. SPRUH73H – October 2011 – Revised April 2013 Enhanced Direct Memory Access (EDMA) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 896: Expected Number Of Transfers For Non-Null Transfer
The null link value is defined as FFFFh. See Section 11.3.3.7 for more details. Enhanced Direct Memory Access (EDMA) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 897 DMA channels to be mapped to any of the PaRAM sets in the PaRAM memory map. Figure 11- illustrates the use of DCHMAP. There is one DCHMAP register per channel. SPRUH73H – October 2011 – Revised April 2013 Enhanced Direct Memory Access (EDMA) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 898: Dma Channel And Qdma Channel To Param Mapping
QCHMAP for a particular QDMA channel. By default, QDMA channels are mapped to PaRAM set 0. You must appropriately re-map PaRAM set 0 before you use it. Enhanced Direct Memory Access (EDMA) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 899: Qdma Channel To Param Mapping
11-25) for the complete global and shadow region memory maps. Figure 11-15 illustrates the conceptual view of the regions. SPRUH73H – October 2011 – Revised April 2013 Enhanced Direct Memory Access (EDMA) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 900: Shadow Region Registers
These registers are user-programmed per region to assign ownership of the DMA/QDMA channels to a region. Enhanced Direct Memory Access (EDMA) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 901 If intermediate transfer completion chaining (ITCCHEN = 1 in OPT) is enabled, the chain-triggered event occurs after every transfer request, except the last of channel m is either submitted or completed SPRUH73H – October 2011 – Revised April 2013 Enhanced Direct Memory Access (EDMA) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 902: Chain Event Triggers
EDMA3 interrupt generation. The software architecture should either use the global interrupt or the shadow interrupts, but not both. Enhanced Direct Memory Access (EDMA) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 903: Transfer Complete Code (Tcc) To Edma3Cc Interrupt Mapping
4 (All but the last TR) TCINTEN = 1, ITCINTEN = 1 20 (All TRs) 5 (All TRs) SPRUH73H – October 2011 – Revised April 2013 Enhanced Direct Memory Access (EDMA) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 904: Interrupt Diagram
EDMA3CC_INT2 : (IPR.E0 & IER.E0 & DRAE2.E0) | (IPR.E1 & IER.E1 & DRAE2.E1) | …|(IPRH.E63 & IERH.E63 & DRAHE2.E63)..Enhanced Direct Memory Access (EDMA) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 905 (b) If IPR/IPRH is equal to 0, this should assure you that all of the enabled interrupts are inactive. SPRUH73H – October 2011 – Revised April 2013 Enhanced Direct Memory Access (EDMA) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 906 NOTE: While using IEVAL for shadow region completion interrupts, you should make sure that the IEVAL operated upon is from that particular shadow region memory map. Enhanced Direct Memory Access (EDMA) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 907: Error Interrupt Operation
Figure 11-17. Error Interrupt Operation EMR/EMRH QEMR CCERR ..EEVAL.EVAL Eval/ pulse EDMACC_ERRINT SPRUH73H – October 2011 – Revised April 2013 Enhanced Direct Memory Access (EDMA) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 908: Allowed Accesses
2E00h-2FFCh 8th octant 7800h-7FFCh The PARAM region is divided into 8 regions referred to as an octant. 908 Enhanced Direct Memory Access (EDMA) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 909: Example Access Denied
5. Remember that accesses to shadow region registers are masked by their respective DRAE register. In this example, the DRAE[7] is set of 0x9FF00FC2. 6. The value finally written to EER is 0x8BC00102. SPRUH73H – October 2011 – Revised April 2013 Enhanced Direct Memory Access (EDMA) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 910 L2 page and the destination buffer on an L1D page. The PRIV is 0 for user-level and the CPU has a PRIVID of 0. The PaRAM set is shown in Figure 11-18. Enhanced Direct Memory Access (EDMA) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 911: Param Set Content For Proxy Memory Protection Example
PRIV and PRIVID at the boundaries of all the interacting entities (CPU, EDMA3CC, EDMA3TC, and slave memories). SPRUH73H – October 2011 – Revised April 2013 Enhanced Direct Memory Access (EDMA) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 912: Proxy Memory Protection Example
(QDMANUM). The mapping of DMA/QDMA channels is critical to achieving the desired performance level for the EDMA and most importantly, in meeting real-time deadlines. See Section 11.3.11.4. Enhanced Direct Memory Access (EDMA) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 913 Therefore, the priority of unloading queues has a secondary affect compared to the priority of the transfers as they are executed by the EDMA3TC (dictated by the priority set using QUEPRI). SPRUH73H – October 2011 – Revised April 2013 Enhanced Direct Memory Access (EDMA) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 914: Read/Write Command Optimization Rules
TR pipelining is useful for maintaining throughput on back-to-back small TRs. It minimizes the startup overhead because reads start in the background of a previous TR writes. Enhanced Direct Memory Access (EDMA) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 915 Detection of a constant addressing mode TR violating the constant addressing mode transfer rules (the source/destination addresses and source/destination indexes must be aligned to 32 bytes). SPRUH73H – October 2011 – Revised April 2013 Enhanced Direct Memory Access (EDMA) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 916: Edma3 Transfer Controller Configurations
16 bytes 16 bytes 16 bytes DSTREGDEPTH 4 entries 4 entries 4 entries 4 entries Configurable Configurable Configurable Configurable Enhanced Direct Memory Access (EDMA) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 917 If a DMA and QDMA event occurs simultaneously, the DMA event always has prioritization against the QDMA event for submission to the event queues. SPRUH73H – October 2011 – Revised April 2013 Enhanced Direct Memory Access (EDMA) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 918 Events continue to be latched and processed and transfer requests continue to be submitted and serviced. Enhanced Direct Memory Access (EDMA) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 919: Edma3 Prioritization
Error Completion From protection detection interrupt EDMA3TC3 EDMA3CC_ Read/ EDMA3CC_ EDMA3CC_INT[0:7] MPINT write to/ ERRINT from EDMA3 programmer SPRUH73H – October 2011 – Revised April 2013 Enhanced Direct Memory Access (EDMA) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 920: Block Move Example
0000h 0000h Destination CCNT Index (DSTCIDX) Source CCNT Index (SRCCIDX) 0000h 0001h Reserved Count for 3rd Dimension (CCNT) Enhanced Direct Memory Access (EDMA) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 921: Subframe Extraction Example
0000h 0000h Destination CCNT Index (DSTCIDX) Source CCNT Index (SRCCIDX) 0000h 0001h Reserved Count for 3rd Dimension (CCNT) SPRUH73H – October 2011 – Revised April 2013 Enhanced Direct Memory Access (EDMA) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 922: Data Sorting Example
C_1022 C_1023 C_1024 D_1022 D_1023 D_1024 A_1022 B_1022 C_1022 D_1022 A_1023 B_1023 C_1023 D_1023 A_1024 B_1024 C_1024 D_1024 Enhanced Direct Memory Access (EDMA) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 923: Data Sorting Example Param Configuration
Based on the premise that serial data is typically a high priority, the EDMA3 channel should be programmed to be on queue 0. SPRUH73H – October 2011 – Revised April 2013 Enhanced Direct Memory Access (EDMA) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 924: Servicing Incoming Mcasp Data Example
(b) Channel Options Parameter (OPT) Content 0000 PRIV Reserved PRIVID ITCCHEN TCCHEN ITCINTEN TCINTEN Reserved 0000 0000 TCCMOD FWID Reserved STATIC SYNCDIM Enhanced Direct Memory Access (EDMA) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 925: Servicing Peripheral Burst Example
Destination Address + 95600h 478_1 478_2 478_639 478_640 Destination Address + 95B00h 479_1 479_2 479_3 479_638 479_639 479_640 SPRUH73H – October 2011 – Revised April 2013 Enhanced Direct Memory Access (EDMA) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 926: Servicing Peripheral Burst Example Param Configuration
(b) Channel Options Parameter (OPT) Content 0000 PRIV Reserved PRIVID ITCCHEN TCCHEN ITCINTEN TCINTEN Reserved 0000 0000 TCCMOD FWID Reserved STATIC SYNCDIM Enhanced Direct Memory Access (EDMA) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 927: Servicing Continuous Mcasp Data Example
McASP TX Register A9o A10o A11o A12o A13o Stream B Source Address B7o B8o B9o B10o B11o B12o B13o SPRUH73H – October 2011 – Revised April 2013 Enhanced Direct Memory Access (EDMA) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 928: Servicing Continuous Mcasp Data Example Param Configuration
(d) Channel Options Parameter (OPT) Content for Transmit Channel (PaRAM Set 12) 0000 PRIV Reserved PRIVID ITCCHEN TCCHEN ITCINTEN TCINTEN Reserved 0001 0000 TCCMOD FWID Reserved STATIC SYNCDIM Enhanced Direct Memory Access (EDMA) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 929: Servicing Continuous Mcasp Data Example Reload Param Configuration
(d) Channel Options Parameter (OPT) Content for Transmit Channel (PaRAM Set 65) 0000 PRIV Reserved PRIVID ITCCHEN TCCHEN ITCINTEN TCINTEN Reserved 0001 0000 TCCMOD FWID Reserved STATIC SYNCDIM SPRUH73H – October 2011 – Revised April 2013 Enhanced Direct Memory Access (EDMA) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 930 CPU. By doing this, the CPU could service a background task while waiting for the EDMA3 to complete. Enhanced Direct Memory Access (EDMA) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 931: Ping-Pong Buffering For Mcasp Data Example
(b) Channel Options Parameter (OPT) Content for Channel 15 0000 PRIV Reserved PRIVID ITCCHEN TCCHEN ITCINTEN TCINTEN Reserved 1101 0000 TCCMOD FWID Reserved STATIC SYNCDIM SPRUH73H – October 2011 – Revised April 2013 Enhanced Direct Memory Access (EDMA) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 932: Ping-Pong Buffering For Mcasp Example Pong Param Configuration
0000h 0000h Destination CCNT Index (DSTCIDX) Source CCNT Index (SRCCIDX) 0000h 0001h Reserved Count for 3rd Dimension (CCNT) Enhanced Direct Memory Access (EDMA) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 933: Ping-Pong Buffering For Mcasp Example Ping Param Configuration
(IPR), which can generate an interrupt to the CPU, if the I8 bit in the interrupt enable register (IER) is set. SPRUH73H – October 2011 – Revised April 2013 Enhanced Direct Memory Access (EDMA) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 934: Intermediate Transfer Completion Chaining Example
Figure 11-40 shows the EDMA3 setup and illustration of an example single large block transfer. Enhanced Direct Memory Access (EDMA) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 935: Single Large Block Transfer Example
BCNT = 16 CCNT = 1 OPT.SYNCDIM = A SYNC OPT.ITCCHEN = 1 OPT.TCINTEN = 1 OPT.TCC = 25 SPRUH73H – October 2011 – Revised April 2013 Enhanced Direct Memory Access (EDMA) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 936: Direct Mapped
SPIXEVT0 McSPI1 SPIREVT0 McSPI1 SPIXEVT1 McSPI1 pr1_host_intr[0:7] corresponds to Host-2 to Host-9 of the PRU-ICSS interrupt controller. 936 Enhanced Direct Memory Access (EDMA) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 937: Crossbar Mapped
Open Open Open Open Open Open Open Open Open TINT0 Timer 0 TINT2 Timer 2 TINT3 Timer 3 SPRUH73H – October 2011 – Revised April 2013 Enhanced Direct Memory Access (EDMA) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 938 Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Enhanced Direct Memory Access (EDMA) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 939: Edmacc Registers
DMA Region Access Enable Register for Region 4 Section 11.4.1.3.1 0364h DRAEH4 DMA Region Access Enable Register High for Region 4 Section 11.4.1.3.1 SPRUH73H – October 2011 – Revised April 2013 Enhanced Direct Memory Access (EDMA) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 940 Interrupt Evaluate Register Section 11.4.1.7.6 1080h QDMA Event Register Section 11.4.1.8.1 1084h QEER QDMA Event Enable Register Section 11.4.1.8.2 940 Enhanced Direct Memory Access (EDMA) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 941 Shadow Region 1 Channel Registers 2400h-2494h Shadow Region 2 Channel Registers 2E00h-2E94h Shadow Channel Registers for MP Space 7 SPRUH73H – October 2011 – Revised April 2013 Enhanced Direct Memory Access (EDMA) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 942: Peripheral Id Register (Pid)
Field Value Description 31-0 40014C00h Peripheral identifier uniquely identifies the EDMA3CC and the specific revision of the EDMA3CC. Enhanced Direct Memory Access (EDMA) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 943: Edma3Cc Configuration Register (Cccfg)
Reserved Reserved. 14-12 NUM_PAENTRY 0-7h Number of PaRAM sets. 0-3h Reserved. 256 PaRAM sets. 5h-7h Reserved. Reserved Reserved. SPRUH73H – October 2011 – Revised April 2013 Enhanced Direct Memory Access (EDMA) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 944 8 QDMA channels. 5h-7h Reserved. Reserved Reserved. NUM_DMACH 0-7h Number of DMA channels. 0-4h Reserved. 64 DMA channels. 6h-7h Reserved. Enhanced Direct Memory Access (EDMA) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 945: Edma3Cc System Configuration Register (Sysconfig)
IP module's internal requirements. IP module shall not generate (IRQ- or DMA-request-related) wakeup events. 0x3 = Reserved. Reserved Reserved. Reserved Reserved. SPRUH73H – October 2011 – Revised April 2013 Enhanced Direct Memory Access (EDMA) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 946: Dma Channel Map N Registers (Dchmapn)
31-14 Reserved Reserved 13-5 PAENTRY 0-1FFh Points to the PaRAM set number for DMA channel n. Reserved Reserved Enhanced Direct Memory Access (EDMA) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 947: Qdma Channel Map N Registers (Qchmapn)
Reserved. Always write 0 to this bit; writes of 1 to this bit are not supported and attempts to do so may result in undefined behavior. SPRUH73H – October 2011 – Revised April 2013 Enhanced Direct Memory Access (EDMA) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 948: Dma Channel Queue N Number Registers (Dmaqnumn)
EDMA3CC to submit the associated QDMA event to any of the event queues in the EDMA3CC. The QDMAQNUM is shown in Figure 11-48 and described in Table 11-33. Enhanced Direct Memory Access (EDMA) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 949: Qdma Channel Queue Number Register (Qdmaqnum)
Event n is queued on Q1. Event n is queued on Q2. Event n is queued on Q3. 4h-7h Reserved. SPRUH73H – October 2011 – Revised April 2013 Enhanced Direct Memory Access (EDMA) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 950: Queue Priority Register (Quepri)
Priority level for queue 0. Dictates the priority level used by TC0 relative to other masters in the device. A value of 0 means highest priority and a value of 7 means lowest priority. Enhanced Direct Memory Access (EDMA) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 951: Event Missed Register (Emr)
Channel 32–63 event missed. En is cleared by writing a 1 to the corresponding bit in the event missed clear register high (EMCRH). No missed event. Missed event occurred. SPRUH73H – October 2011 – Revised April 2013 Enhanced Direct Memory Access (EDMA) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 952: Event Missed Clear Register (Emcr)
No effect. Corresponding missed event bit in the event missed register high (EMRH) is cleared (En = 0). Enhanced Direct Memory Access (EDMA) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 953: Qdma Event Missed Register (Qemr)
Channel 0-7 QDMA event missed. En is cleared by writing a 1 to the corresponding bit in the QDMA event missed clear register (QEMCR). No missed event. Missed event occurred. SPRUH73H – October 2011 – Revised April 2013 Enhanced Direct Memory Access (EDMA) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 954: Qdma Event Missed Clear Register (Qemcr)
Figure 11-56. EDMA3CC Error Register (CCERR) Reserved TCCERR Reserved QTHRXCD3 QTHRXCD2 QTHRXCD1 QTHRXCD0 LEGEND: R = Read only; -n = value after reset Enhanced Direct Memory Access (EDMA) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 955: Edma3Cc Error Clear Register (Ccerrclr)
TCCERR Transfer completion code error clear. No effect. Clears the TCCERR bit in the EDMA3CC error register (CCERR). SPRUH73H – October 2011 – Revised April 2013 Enhanced Direct Memory Access (EDMA) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 956 Clears the QTHRXCD0 bit in the EDMA3CC error register (CCERR) and the WM and THRXCD bits in the queue status register 0 (QSTAT0). Enhanced Direct Memory Access (EDMA) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 957: Error Evaluation Register (Eeval)
EDMA3CC error interrupt will be pulsed if any errors have not been cleared in any of the error registers (EMR/EMRH, QEMR, or CCERR). SPRUH73H – October 2011 – Revised April 2013 Enhanced Direct Memory Access (EDMA) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 958: Dma Region Access Enable Register For Region M (Draem)
QDMA registers. This includes all 4-bit QDMA registers. The QRAEm is shown in Figure 11-61 and described in Table 11-45. Enhanced Direct Memory Access (EDMA) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 959: Qdma Region Access Enable For Region M (Qraem)32-Bit, 2 Rows
Accesses via region m address space to bit n in any QDMA channel register are allowed. Reads return the value from bit n and writes modify the state of bit n. SPRUH73H – October 2011 – Revised April 2013 Enhanced Direct Memory Access (EDMA) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 960: Event Queue Entry Registers (Qxey)
Event entry y in queue x. Event number: 0-3h QDMA channel number (0 to 3). 0-3Fh DMA channel/event number (0 to 63). Enhanced Direct Memory Access (EDMA) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 961: Queue Status Register N (Qstatn)
Start pointer. The offset to the head entry of queue n, in units of entries. Always enabled. Legal values are 0 (0th entry) to Fh (15th entry). SPRUH73H – October 2011 – Revised April 2013 Enhanced Direct Memory Access (EDMA) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 962: Queue Watermark Threshold A Register (Qwmthra)
0 at an instant in time (visible via the NUMVAL bit in QSTAT0) equals or exceeds the value specified by Q0. 0-10h The default is 16 (maximum allowed). Disables the threshold errors. 12h-1Fh Reserved. Enhanced Direct Memory Access (EDMA) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 963: Edma3Cc Status Register (Ccstat)
Reserved. Always write 0 to this bit; writes of 1 to this bit are not supported and attempts to do so may result in undefined behavior. SPRUH73H – October 2011 – Revised April 2013 Enhanced Direct Memory Access (EDMA) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 964 No enabled DMA events are active within the EDMA3CC. At least one enabled DMA event (ER and EER, ESR, CER) is active within the EDMA3CC. Enhanced Direct Memory Access (EDMA) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 965: Memory Protection Fault Address Register (Mpfar)
This register can only be cleared via the memory protection fault command register (MPFCR). SPRUH73H – October 2011 – Revised April 2013 Enhanced Direct Memory Access (EDMA) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 966: Memory Protection Fault Status Register (Mpfsr)
User execute error. No error detected. User level task attempted to execute from a MP page without UX permissions. Enhanced Direct Memory Access (EDMA) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 967: Memory Protection Fault Command Register (Mpfcr)
CPU write of 1 to the MPFCLR bit causes any error conditions stored in the memory protection fault address register (MPFAR) and the memory protection fault status register (MPFSR) to be cleared. SPRUH73H – October 2011 – Revised April 2013 Enhanced Direct Memory Access (EDMA) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 968: Memory Protection Page Attribute Register (Mppan)
User execute accesses are not allowed from region M. User execute accesses are allowed from region M addresses. Enhanced Direct Memory Access (EDMA) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 969 The Debug List table provides the type of synchronization events and the EDMA3CC channels associated to each of these external events. SPRUH73H – October 2011 – Revised April 2013 Enhanced Direct Memory Access (EDMA) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 970: Event Register (Er)
EDMA3CC event is asserted. Corresponding DMA event is prioritized versus other pending DMA/QDMA events for submission to the EDMA3TC. Enhanced Direct Memory Access (EDMA) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 971: Event Clear Register (Ecr)
(ERH). A write of 0 has no effect. No effect. EDMA3CC event is cleared in the event register high (ERH). SPRUH73H – October 2011 – Revised April 2013 Enhanced Direct Memory Access (EDMA) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 972: Event Set Register (Esr)
Event set for event 0-31. No effect. Corresponding DMA event is prioritized versus other pending DMA/QDMA events for submission to the EDMA3TC. Enhanced Direct Memory Access (EDMA) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 973: Event Set Register High (Esrh)
Event set for event 32-63. No effect. Corresponding DMA event is prioritized versus other pending DMA/QDMA events for submission to the EDMA3TC. SPRUH73H – October 2011 – Revised April 2013 Enhanced Direct Memory Access (EDMA) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 974: Chained Event Register (Cer)
EDMA3TC. Figure 11-77. Chained Event Register High (CERH) LEGEND: R = Read only; -n = value after reset Enhanced Direct Memory Access (EDMA) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 975: Chained Event Register High (Cerh) Field Descriptions
Chained event set for event 32-63. No effect. Corresponding DMA event is prioritized versus other pending DMA/QDMA events for submission to the EDMA3TC. SPRUH73H – October 2011 – Revised April 2013 Enhanced Direct Memory Access (EDMA) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 976: Event Enable Register (Eer)
Event is enabled. An external event latched in the event register high (ERH) is evaluated by the EDMA3CC. Enhanced Direct Memory Access (EDMA) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 977: Event Enable Clear Register (Eecr)
No effect. Event is disabled. Corresponding bit in the event enable register high (EERH) is cleared (En = 0). SPRUH73H – October 2011 – Revised April 2013 Enhanced Direct Memory Access (EDMA) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 978: Event Enable Set Register (Eesr)
No effect. Event is enabled. Corresponding bit in the event enable register high (EERH) is set (En = 1). Enhanced Direct Memory Access (EDMA) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 979: Secondary Event Register (Ser)
Event is not currently stored in the event queue. Event is currently stored in the event queue. Event submission/prioritization logic will not prioritize additional events. SPRUH73H – October 2011 – Revised April 2013 Enhanced Direct Memory Access (EDMA) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 980: Secondary Event Clear Register (Secr)
Secondary event clear register. No effect. Corresponding bit in the secondary event registers high (SERH) is cleared (En = 0). Enhanced Direct Memory Access (EDMA) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 981: Interrupt Enable Register (Ier)
IECR/IECRH clear the corresponding interrupt bits in the interrupt enable registers (IER/IERH); writes of 0 have no effect. SPRUH73H – October 2011 – Revised April 2013 Enhanced Direct Memory Access (EDMA) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 982: Interrupt Enable Clear Register (Iecr)
Interrupt enable clear for channels 32-63. No effect. Corresponding bit in the interrupt enable register high (IERH) is cleared (In = 0). Enhanced Direct Memory Access (EDMA) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 983: Interrupt Enable Set Register (Iesr)
Interrupt enable clear for channels 32-63. No effect. Corresponding bit in the interrupt enable register high (IERH) is set (In = 1). SPRUH73H – October 2011 – Revised April 2013 Enhanced Direct Memory Access (EDMA) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 984: Interrupt Pending Register (Ipr)
Writes of 0 have no effect. All set bits in IPR/IPRH must be cleared to allow EDMA3CC to assert additional transfer completion interrupts. Enhanced Direct Memory Access (EDMA) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 985: Interrupt Clear Register (Icr)
Interrupt clear register for TCC = 32-63. No effect. Corresponding bit in the interrupt pending register high (IPRH) is cleared (In = 0). SPRUH73H – October 2011 – Revised April 2013 Enhanced Direct Memory Access (EDMA) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 986: Interrupt Evaluate Register (Ieval)
EVAL bit in IEVAL pulses the global completion interrupt, but writing to the EVAL bit in IEVAL0 pulses the region 0 completion interrupt. Enhanced Direct Memory Access (EDMA) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 987: Qdma Event Register (Qer)
QDMA event for channels 0-7. No effect. Corresponding QDMA event is prioritized versus other pending DMA/QDMA events for submission to the EDMA3TC. SPRUH73H – October 2011 – Revised April 2013 Enhanced Direct Memory Access (EDMA) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 988: Qdma Event Enable Register (Qeer)
QDMA channel n is enabled. QDMA events will be recognized and will get latched in the QDMA event register (QER). Enhanced Direct Memory Access (EDMA) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 989: Qdma Event Enable Clear Register (Qeecr)
QDMA event is disabled. Corresponding bit in the QDMA event enable register (QEER) is cleared (En = 0). SPRUH73H – October 2011 – Revised April 2013 Enhanced Direct Memory Access (EDMA) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 990: Qdma Event Enable Set Register (Qeesr)
QDMA event is enabled. Corresponding bit in the QDMA event enable register (QEER) is set (En = 1). Enhanced Direct Memory Access (EDMA) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 991: Qdma Secondary Event Register (Qser)
QDMA event is not currently stored in the event queue. QDMA event is currently stored in the event queue. EDMA3CC will not prioritize additional events. SPRUH73H – October 2011 – Revised April 2013 Enhanced Direct Memory Access (EDMA) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 992: Qdma Secondary Event Clear Register (Qsecr)
Corresponding bit in the QDMA secondary event register (QSER) and the QDMA event register (QER) is cleared (En = 0). Enhanced Direct Memory Access (EDMA) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 993: Edma3Tc Registers
DFCNT3 Destination FIFO Count Register 3 Section 11.4.2.7.12 03CCh DFDST3 Destination FIFO Destination Address Register 3 Section 11.4.2.7.13 SPRUH73H – October 2011 – Revised April 2013 Enhanced Direct Memory Access (EDMA) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 994: Peripheral Id Register (Pid)
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 11-90. Peripheral ID Register (PID) Field Descriptions Field Value Description 31-0 40007C00 Peripheral identifier. Enhanced Direct Memory Access (EDMA) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 995: Edma3Tc Configuration Register (Tccfg)
128-bit Reserved. Reserved Reserved. FIFOSIZE 0-7h FIFO size 0-1h Reserved. Reserved. Reserved. 512 byte FIFO Reserved. 6h-7h Reserved. SPRUH73H – October 2011 – Revised April 2013 Enhanced Direct Memory Access (EDMA) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 996: Edma3Tc System Configuration Register (Sysconfig)
IP module's internal requirements. IP module shall not generate (IRQ or DMA-request-related) wakeup events. 0x3 = Reserved. Reserved Reserved. Enhanced Direct Memory Access (EDMA) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 997: Edma3Tc Channel Status Register (Tcstat)
Source controller is idle. Source active register set contains a previously processed transfer request. Source controller is busy servicing a transfer request. SPRUH73H – October 2011 – Revised April 2013 Enhanced Direct Memory Access (EDMA) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 998 Program register set busy Program set idle and is available for programming by the EDMA3CC. Program set busy Enhanced Direct Memory Access (EDMA) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 999: Error Register (Errstat)
EDMA3TC has detected an error at source or destination address. Error information can be read from the error details register (ERRDET). SPRUH73H – October 2011 – Revised April 2013 Enhanced Direct Memory Access (EDMA) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...
Page 1000: Error Enable Register (Erren)
Interrupt enable for bus error (BUSERR). BUSERR is disabled. BUSERR is enabled and contributes to the state of EDMA3TC error interrupt generation. 1000 Enhanced Direct Memory Access (EDMA) SPRUH73H – October 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated...