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Table 6-94. Ethernet Media Access Controller (EMAC) Registers (continued)
BYTE ADDRESS
0x01E2 3140
0x01E2 3144
0x01E2 3148
0x01E2 314C
0x01E2 3150
0x01E2 3154
0x01E2 3158
0x01E2 315C
0x01E2 3160
0x01E2 3164
0x01E2 3168
0x01E2 316C
0x01E2 3170
0x01E2 3174
0x01E2 31D0
0x01E2 31D4
0x01E2 31D8
0x01E2 31DC
0x01E2 31E0
0x01E2 31E4
0x01E2 31E8
0x01E2 31EC
0x01E2 3200 - 0x01E2 32FC
0x01E2 3500
0x01E2 3504
0x01E2 3508
0x01E2 3600
0x01E2 3604
0x01E2 3608
0x01E2 360C
0x01E2 3610
0x01E2 3614
0x01E2 3618
0x01E2 361C
0x01E2 3620
0x01E2 3624
0x01E2 3628
0x01E2 362C
0x01E2 3630
0x01E2 3634
0x01E2 3638
0x01E2 363C
0x01E2 3640
0x01E2 3644
0x01E2 3648
0x01E2 364C
0x01E2 3650
Copyright © 2010–2014, Texas Instruments Incorporated
ACRONYM
RX0FREEBUFFER
Receive Channel 0 Free Buffer Count Register
RX1FREEBUFFER
Receive Channel 1 Free Buffer Count Register
RX2FREEBUFFER
Receive Channel 2 Free Buffer Count Register
RX3FREEBUFFER
Receive Channel 3 Free Buffer Count Register
RX4FREEBUFFER
Receive Channel 4 Free Buffer Count Register
RX5FREEBUFFER
Receive Channel 5 Free Buffer Count Register
RX6FREEBUFFER
Receive Channel 6 Free Buffer Count Register
RX7FREEBUFFER
Receive Channel 7 Free Buffer Count Register
MACCONTROL
MAC Control Register
MACSTATUS
MAC Status Register
EMCONTROL
Emulation Control Register
FIFOCONTROL
FIFO Control Register
MACCONFIG
MAC Configuration Register
SOFTRESET
Soft Reset Register
MACSRCADDRLO
MAC Source Address Low Bytes Register
MACSRCADDRHI
MAC Source Address High Bytes Register
MACHASH1
MAC Hash Address Register 1
MACHASH2
MAC Hash Address Register 2
BOFFTEST
Back Off Test Register
TPACETEST
Transmit Pacing Algorithm Test Register
RXPAUSE
Receive Pause Timer Register
TXPAUSE
Transmit Pause Timer Register
(see
Table
6-95)
EMAC Statistics Registers
MACADDRLO
MAC Address Low Bytes Register, Used in Receive Address Matching
MACADDRHI
MAC Address High Bytes Register, Used in Receive Address Matching
MACINDEX
MAC Index Register
TX0HDP
Transmit Channel 0 DMA Head Descriptor Pointer Register
TX1HDP
Transmit Channel 1 DMA Head Descriptor Pointer Register
TX2HDP
Transmit Channel 2 DMA Head Descriptor Pointer Register
TX3HDP
Transmit Channel 3 DMA Head Descriptor Pointer Register
TX4HDP
Transmit Channel 4 DMA Head Descriptor Pointer Register
TX5HDP
Transmit Channel 5 DMA Head Descriptor Pointer Register
TX6HDP
Transmit Channel 6 DMA Head Descriptor Pointer Register
TX7HDP
Transmit Channel 7 DMA Head Descriptor Pointer Register
RX0HDP
Receive Channel 0 DMA Head Descriptor Pointer Register
RX1HDP
Receive Channel 1 DMA Head Descriptor Pointer Register
RX2HDP
Receive Channel 2 DMA Head Descriptor Pointer Register
RX3HDP
Receive Channel 3 DMA Head Descriptor Pointer Register
RX4HDP
Receive Channel 4 DMA Head Descriptor Pointer Register
RX5HDP
Receive Channel 5 DMA Head Descriptor Pointer Register
RX6HDP
Receive Channel 6 DMA Head Descriptor Pointer Register
RX7HDP
Receive Channel 7 DMA Head Descriptor Pointer Register
TX0CP
Transmit Channel 0 Completion Pointer Register
TX1CP
Transmit Channel 1 Completion Pointer Register
TX2CP
Transmit Channel 2 Completion Pointer Register
TX3CP
Transmit Channel 3 Completion Pointer Register
TX4CP
Transmit Channel 4 Completion Pointer Register
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Product Folder Links:
SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
REGISTER DESCRIPTION
Peripheral Information and Electrical Specifications
AM1808
AM1808
187
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