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AHCLKR/X (Falling Edge Polarity)
AHCLKR/X (Rising Edge Polarity)
ACLKR/X (CLKRP = CLKXP = 1)
ACLKR/X (CLKRP = CLKXP = 0)
AFSR/X (Bit Width, 0 Bit Delay)
AFSR/X (Bit Width, 1 Bit Delay)
AFSR/X (Bit Width, 2 Bit Delay)
AFSR/X (Slot Width, 0 Bit Delay)
AFSR/X (Slot Width, 1 Bit Delay)
AFSR/X (Slot Width, 2 Bit Delay)
AXR[n] (Data Out/Transmit)
A.
For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP
receiver is configured for rising edge (to shift data in).
B.
For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP
receiver is configured for falling edge (to shift data in).
Copyright © 2010–2014, Texas Instruments Incorporated
10
10
9
11
12
(A)
(B)
13
13
13
A0
A1
Figure 6-31. McASP Output Timings
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SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
12
13
A30 A31
B0 B1
B30 B31 C0
Peripheral Information and Electrical Specifications
AM1808
AM1808
13
13
13
14
15
C1 C2 C3
C31
141
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