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AM1808
SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
6.26.2 uPP Electrical Data/Timing
Table 6-116. Timing Requirements for uPP (see
NO.
1
t
Cycle time, CHn_CLK
c(INCLK)
2
t
Pulse width, CHn_CLK high
w(INCLKH)
3
t
Pulse width, CHn_CLK low
w(INCLKL)
4
t
Setup time, CHn_START valid before CHn_CLK high
su(STV-INCLKH)
5
t
Hold time, CHn_START valid after CHn_CLK high
h(INCLKH-STV)
6
t
Setup time, CHn_ENABLE valid before CHn_CLK high
su(ENV-INCLKH)
7
t
Hold time, CHn_ENABLE valid after CHn_CLK high
h(INCLKH-ENV)
Setup time, CHn_DATA/XDATA valid before CHn_CLK
8
t
su(DV-INCLKH)
high
9
t
Hold time, CHn_DATA/XDATA valid after CHn_CLK high
h(INCLKH-DV)
Setup time, CHn_DATA/XDATA valid before CHn_CLK
10
t
su(DV-INCLKL)
low
11
t
Hold time, CHn_DATA/XDATA valid after CHn_CLK low
h(INCLKL-DV)
19
t
Setup time, CHn_WAIT valid before CHn_CLK high
su(WTV-INCLKL)
20
t
Hold time, CHn_WAIT valid after CHn_CLK high
h(INCLKL-WTV)
21
t
Cycle time, 2xTXCLK input clock
c(2xTXCLK)
(1) 2xTXCLK is an alternate transmit clock source that must be at least 2 times the required uPP transmit clock rate (as it is is divided down
by 2 inside the uPP). 2xTXCLK has no specified skew relationship to the CHn_CLOCK and therefore is not shown in the timing diagram.
Table 6-117. Switching Characteristics Over Recommended Operating Conditions for uPP
NO.
12
t
Cycle time, CHn_CLK
c(OUTCLK)
13
t
Pulse width, CHn_CLK high
w(OUTCLKH)
14
t
Pulse width, CHn_CLK low
w(OUTCLKL)
15
t
Delay time, CHn_START valid after CHn_CLK high
d(OUTCLKH-STV)
16
t
Delay time, CHn_ENABLE valid after CHn_CLK high
d(OUTCLKH-ENV)
17
t
Delay time, CHn_DATA/XDATA valid after CHn_CLK high
d(OUTCLKH-DV)
18
t
Delay time, CHn_DATA/XDATA valid after CHn_CLK low
d(OUTCLKL-DV)
220
Peripheral Information and Electrical Specifications
Figure
SDR mode
DDR mode
SDR mode
DDR mode
SDR mode
DDR mode
(1)
PARAMETER
SDR mode
DDR mode
SDR mode
DDR mode
SDR mode
DDR mode
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6-69,
Figure
6-70,
Figure
1.3V, 1.2V
1.1V
MIN
MAX
MIN
13.33
20
26.66
40
5
8
10
16
5
8
10
16
4
5.5
0.8
0.8
4
5.5
0.8
0.8
4
5.5
0.8
0.8
4
5.5
0.8
0.8
10
12
0.8
0.8
6.66
10
1.3V, 1.2V
1.1V
MIN
MAX
MIN
13.33
20
26.66
40
5
8
10
16
5
8
10
16
2
11
2
2
11
2
2
11
2
2
11
2
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AM1808
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6-71,
Figure
6-72)
1.0V
UNIT
MAX
MIN
MAX
26.66
ns
53.33
10
ns
20
10
ns
20
6.5
ns
0.8
ns
6.5
ns
0.8
ns
6.5
ns
0.8
ns
6.5
ns
0.8
ns
14
ns
0.8
ns
13.33
ns
1.0V
UNIT
MAX
MIN
MAX
26.66
ns
53.33
10
ns
20
10
ns
20
15
2
21
ns
15
2
21
ns
15
2
21
ns
15
2
21
ns
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