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AM1808
SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
Table 6-22. Switching Characteristics for EMIFA Asynchronous Memory Interface
NO.
1
t
Turn around time
d(TURNAROUND)
EMIF read cycle time (EW = 0)
3
t
c(EMRCYCLE)
EMIF read cycle time (EW = 1)
Output setup time, EMA_CE[5:2] low to EMA_OE low (SS = 0)
4
t
su(EMCEL-EMOEL)
Output setup time, EMA_CE[5:2] low to EMA_OE low (SS = 1)
Output hold time, EMA_OE high to EMA_CE[5:2] high (SS = 0)
5
t
h(EMOEH-EMCEH)
Output hold time, EMA_OE high to EMA_CE[5:2] high (SS = 1)
6
t
Output setup time, EMA_BA[1:0] valid to EMA_OE low
su(EMBAV-EMOEL)
7
t
Output hold time, EMA_OE high to EMA_BA[1:0] invalid
h(EMOEH-EMBAIV)
8
t
Output setup time, EMA_A[13:0] valid to EMA_OE low
su(EMBAV-EMOEL)
9
t
Output hold time, EMA_OE high to EMA_A[13:0] invalid
h(EMOEH-EMAIV)
EMA_OE active low width (EW = 0)
10
t
w(EMOEL)
EMA_OE active low width (EW = 1)
11
t
Delay time from EMA_WAIT deasserted to EMA_OE high
d(EMWAITH-EMOEH)
28
t
Output setup time, EMA_A_RW valid to EMA_OE low
su(EMARW-EMOEL)
29
t
Output hold time, EMA_OE high to EMA_A_RW invalid
h(EMOEH-EMARW)
EMIF write cycle time (EW = 0)
15
t
c(EMWCYCLE)
EMIF write cycle time (EW = 1)
Output setup time, EMA_CE[5:2] low to EMA_WE low (SS = 0)
16
t
su(EMCEL-EMWEL)
Output setup time, EMA_CE[5:2] low to EMA_WE low (SS = 1)
Output hold time, EMA_WE high to EMA_CE[5:2] high (SS = 0)
17
t
h(EMWEH-EMCEH)
Output hold time, EMA_WE high to EMA_CE[5:2] high (SS = 1)
18
t
Output setup time, EMA_BA[1:0] valid to EMA_WE low
su(EMDQMV-EMWEL)
19
t
Output hold time, EMA_WE high to EMA_BA[1:0] invalid
h(EMWEH-EMDQMIV)
20
t
Output setup time, EMA_BA[1:0] valid to EMA_WE low
su(EMBAV-EMWEL)
21
t
Output hold time, EMA_WE high to EMA_BA[1:0] invalid
h(EMWEH-EMBAIV)
(1) TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold, MEWC = Maximum external wait cycles. These
parameters are programmed via the Asynchronous Bank and Asynchronous Wait Cycle Configuration Registers. These support the following range of values: TA[4-1], RS[16-1], RST[64-
1], RH[8-1], WS[16-1], WST[64-1], WH[8-1], and MEW[1-256].
(2) E = EMA_CLK period or in ns. EMA_CLK is selected either as SYSCLK3 or the PLL0 output clock divided by 4.5. As an example, when SYSCLK3 is selected and set to 100MHz,
E=10ns.
(3) EWC = external wait cycles determined by EMA_WAIT input signal. EWC supports the following range of values EWC[256-1]. Note that the maximum wait time before timeout is specified
by bit field MEWC in the Asynchronous Wait Cycle Configuration Register.
104
Peripheral Information and Electrical Specifications
PARAMETER
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MIN
READS and WRITES
(TA)*E - 3
READS
(RS+RST+RH)*E - 3
(RS+RST+RH+EWC)*E - 3
(RS)*E-3
-3
(RH)*E - 3
-3
(RS)*E-3
(RH)*E-3
(RS)*E-3
(RH)*E-3
(RST)*E-3
(RST+EWC)*E-3
3E-3
(RS)*E-3
(RH)*E-3
WRITES
(WS+WST+WH)*E-3
(WS+WST+WH+EWC)*E - 3
(WS)*E - 3
-3
(WH)*E-3
-3
(WS)*E-3
(WH)*E-3
(WS)*E-3
(WH)*E-3
AM1808
(1) (2) (3)
1.3V, 1.2V, 1.1V, 1.0V
Nom
MAX
(TA)*E
(RS+RST+RH)*E
(RS+RST+RH)*E + 3
(RS+RST+RH+EWC)*E
(RS+RST+RH+EWC)*E + 3
(RS)*E
0
(RH)*E
0
(RS)*E
(RH)*E
(RS)*E
(RH)*E
(RST)*E
(RST+EWC)*E
(RST+EWC)*E+3
4E
(RS)*E
(RH)*E
(WS+WST+WH)*E
(WS+WST+WH)*E+3
(WS+WST+WH+EWC)*E +
(WS+WST+WH+EWC)*E
(WS)*E
0
(WH)*E
0
(WS)*E
(WH)*E
(WS)*E
(WH)*E
Copyright © 2010–2014, Texas Instruments Incorporated
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UNIT
(TA)*E + 3
ns
ns
ns
(RS)*E+3
ns
+3
ns
(RH)*E + 3
ns
+3
ns
(RS)*E+3
ns
(RH)*E+3
ns
(RS)*E+3
ns
(RH)*E+3
ns
(RST)*E+3
ns
ns
4E+3
ns
(RS)*E+3
ns
(RH)*E+3
ns
ns
ns
3
(WS)*E + 3
ns
+3
ns
(WH)*E+3
ns
+3
ns
(WS)*E+3
ns
(WH)*E+3
ns
(WS)*E+3
ns
(WH)*E+3
ns
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